PATTGEN Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	67.743us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	17.826us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	42.806us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	288.983us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	28.804us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	28.959us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	42.806us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.804us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.900m	2.662ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	5.141ms	50	50	100.00
V2	error	pattgen_error	13.000s	97.233us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.500m	11.525ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	11.084us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	18.040us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	589.412us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	589.412us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	17.826us	5	5	100.00
		pattgen_csr_rw	3.000s	42.806us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.804us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	20.909us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	17.826us	5	5	100.00
		pattgen_csr_rw	3.000s	42.806us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.804us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	20.909us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	79.032us	20	20	100.00
		pattgen_sec_cm	7.000s	329.567us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	79.032us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	28.317m	351.842ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	1.367m	10.018ms	47	50	94.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

1.pattgen_stress_all_with_rand_reset.62039592757153895386783480032244020607193983529782311677951165989288023955915
Line 630, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17549730163 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 17549738616 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 17549738616 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 17549801772 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.68359553833853445169313526203886505125960132683428289890813076420065091176163
Line 1492, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 66660790270 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 66660793852 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 66660793852 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 66660843852 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 11.pattgen_stress_all_with_rand_reset.65330887120531724907861669340232047370029895924672461385259825350087610383353
    Line 824, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 72599197528 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 24.pattgen_stress_all_with_rand_reset.21303509449080085488880420415558040123229247207523139039622809013870280558116
    Line 696, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28751579073 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 9.pattgen_inactive_level.49978594778553438586409243003267136553142133318304738038371449684875609947774
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10669981665 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x8a602250) == 0x0
  UVM_INFO @ 10669981665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.pattgen_inactive_level.30022724362962582564232271483237141622119751862841159089440028000514917097996
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10017641752 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x49aac390) == 0x0
  UVM_INFO @ 10017641752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 32.pattgen_inactive_level.54942498313822837644883566254196810106325962702544143830428585996208374464472
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10023606117 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc4ec3d90) == 0x0
  UVM_INFO @ 10023606117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```