PATTGEN Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 4.000s 210.217us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 30.266us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 15.073us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 1.004ms 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 15.925us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 4.000s 55.977us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 15.073us 20 20 100.00
pattgen_csr_aliasing 3.000s 15.925us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.767m 3.948ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.867m 2.687ms 50 50 100.00
V2 error pattgen_error 3.000s 19.640us 50 50 100.00
V2 stress_all pattgen_stress_all 2.083m 2.709ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 45.991us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 16.770us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 6.000s 537.950us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 6.000s 537.950us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 30.266us 5 5 100.00
pattgen_csr_rw 3.000s 15.073us 20 20 100.00
pattgen_csr_aliasing 3.000s 15.925us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 57.542us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 30.266us 5 5 100.00
pattgen_csr_rw 3.000s 15.073us 20 20 100.00
pattgen_csr_aliasing 3.000s 15.925us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 57.542us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 3.000s 121.895us 20 20 100.00
pattgen_sec_cm 3.000s 109.363us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 3.000s 121.895us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 31.083m 86.698ms 13 50 26.00
V3 TOTAL 13 50 26.00
Unmapped tests pattgen_inactive_level 5.517m 10.013ms 46 50 92.00
TOTAL 529 570 92.81

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results