PATTGEN Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	210.217us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	30.266us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	15.073us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.004ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	15.925us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	55.977us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	15.073us	20	20	100.00
		pattgen_csr_aliasing	3.000s	15.925us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.767m	3.948ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	2.687ms	50	50	100.00
V2	error	pattgen_error	3.000s	19.640us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.083m	2.709ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	45.991us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	16.770us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	537.950us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	537.950us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	30.266us	5	5	100.00
		pattgen_csr_rw	3.000s	15.073us	20	20	100.00
		pattgen_csr_aliasing	3.000s	15.925us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	57.542us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	30.266us	5	5	100.00
		pattgen_csr_rw	3.000s	15.073us	20	20	100.00
		pattgen_csr_aliasing	3.000s	15.925us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	57.542us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	121.895us	20	20	100.00
		pattgen_sec_cm	3.000s	109.363us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	121.895us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	31.083m	86.698ms	13	50	26.00
V3		TOTAL			13	50	26.00
	Unmapped tests	pattgen_inactive_level	5.517m	10.013ms	46	50	92.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.18897063624906696009886490540144574859571168363456368049869679038190631319312
Line 328, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33120841143 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 33120856243 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 33120856243 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 33121656243 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.81223121579629270407778784779848206714779297717870177203234469010602890543017
Line 623, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 69820706942 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 69820710329 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 69820710329 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 69820790329 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 7 failures:
- Test pattgen_stress_all_with_rand_reset has 7 failures.
  - 4.pattgen_stress_all_with_rand_reset.41437908319468784380800719268717163974685488798875973449082255366708976661747
    Line 332, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5693623241 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 6.pattgen_stress_all_with_rand_reset.39168718160451081349545959291451901793366016338170778189926322430078673285359
    Line 507, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17661748128 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 0.pattgen_inactive_level.2926752489761317406074202762260565270623020285256700656681044741350354730195
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10113807577 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4bdff810) == 0x0
  UVM_INFO @ 10113807577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.pattgen_inactive_level.81726854884646635196094553456030763412608247217877637202201089223402512299745
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10014880854 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf8d81c50) == 0x0
  UVM_INFO @ 10014880854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 23.pattgen_inactive_level.67529950049338821051520721969998337629620715808655079227143348893982566394719
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013009772 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc26dbe50) == 0x0
  UVM_INFO @ 10013009772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.pattgen_inactive_level.94885476068139053979976606658208804198012459355823978481630616893425621884247
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013725840 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd1a88450) == 0x0
  UVM_INFO @ 10013725840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```