PATTGEN Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	201.744us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	28.588us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	18.075us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	495.357us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	13.780us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	83.684us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	18.075us	20	20	100.00
		pattgen_csr_aliasing	3.000s	13.780us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.917m	26.512ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.817m	10.122ms	50	50	100.00
V2	error	pattgen_error	12.000s	34.311us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.933m	4.021ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	14.534us	50	50	100.00
V2	intr_test	pattgen_intr_test	11.000s	15.935us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	18.000s	129.099us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	18.000s	129.099us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	28.588us	5	5	100.00
		pattgen_csr_rw	7.000s	18.075us	20	20	100.00
		pattgen_csr_aliasing	3.000s	13.780us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	13.178us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	28.588us	5	5	100.00
		pattgen_csr_rw	7.000s	18.075us	20	20	100.00
		pattgen_csr_aliasing	3.000s	13.780us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	13.178us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	85.853us	20	20	100.00
		pattgen_sec_cm	4.000s	64.020us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	85.853us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	39.183m	213.362ms	11	50	22.00
V3		TOTAL			11	50	22.00
	Unmapped tests	pattgen_inactive_level	51.000s	10.010ms	47	50	94.00
		TOTAL			528	570	92.63

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

1.pattgen_stress_all_with_rand_reset.105304419710271895976276998755446645608227876276469456590221922572296629246889
Line 310, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1454529720 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1454542266 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1454542266 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 1454580002 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.99582483065891251810780454455681973440235074789274332959270964978038594316847
Line 440, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 47803569563 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 47803574161 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 47803574161 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 47803685273 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 12.pattgen_stress_all_with_rand_reset.45015302473851785229511511952325129690553884389184171643444287797330422623268
    Line 826, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109082783565 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 18.pattgen_stress_all_with_rand_reset.95955470350735999359864390017389574318513640184200452760984505583274173569906
    Line 315, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 206613802 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 29.pattgen_inactive_level.78140180241399862949775597684835223210701586750541020366474934263094391067464
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015886120 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb30f0450) == 0x0
  UVM_INFO @ 10015886120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.pattgen_inactive_level.115264592434925250785167300437887989056655114084847188292167412641044454589613
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009579923 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6b70de50) == 0x0
  UVM_INFO @ 10009579923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 44.pattgen_inactive_level.48816622989704452731458366528587694311803811585837236737315363376481337839962
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10096284542 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7c734450) == 0x0
  UVM_INFO @ 10096284542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```