PATTGEN Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	199.935us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	14.679us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	15.818us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	734.436us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	288.128us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	37.481us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	15.818us	20	20	100.00
		pattgen_csr_aliasing	3.000s	288.128us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.083m	10.539ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	10.955ms	50	50	100.00
V2	error	pattgen_error	8.000s	173.412us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.667m	3.993ms	50	50	100.00
V2	alert_test	pattgen_alert_test	14.000s	14.022us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	26.452us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	106.394us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	106.394us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	14.679us	5	5	100.00
		pattgen_csr_rw	3.000s	15.818us	20	20	100.00
		pattgen_csr_aliasing	3.000s	288.128us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	44.807us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	14.679us	5	5	100.00
		pattgen_csr_rw	3.000s	15.818us	20	20	100.00
		pattgen_csr_aliasing	3.000s	288.128us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	44.807us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	83.446us	20	20	100.00
		pattgen_sec_cm	3.000s	250.216us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	83.446us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.633m	353.325ms	16	50	32.00
V3		TOTAL			16	50	32.00
	Unmapped tests	pattgen_inactive_level	5.500m	10.014ms	45	50	90.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.6940078820050789090470500014534239264150033684044492375339936123960751501882
Line 326, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3934389863 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3934416389 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3934416389 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 3934490463 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.16256206082458158599506573763876091565016171689383141223273954903422166355299
Line 554, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40132153778 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 40132159448 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 40132159448 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 40132534451 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 5.pattgen_stress_all_with_rand_reset.41002932378539422726701660417945804902901603694504043663965441295689055547435
    Line 473, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38149346246 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 30.pattgen_stress_all_with_rand_reset.98524246686111967602054982410656703779951424677830290667876090240958892325818
    Line 324, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13316453699 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 1.pattgen_inactive_level.3884285775158103398277739344428291165143490418521570322553701230444753616834
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10036697730 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3f179ed0) == 0x0
  UVM_INFO @ 10036697730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.pattgen_inactive_level.74251524869398814069467624998193759690393329248680188107505475959826886096558
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10041599768 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc092cb90) == 0x0
  UVM_INFO @ 10041599768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 38.pattgen_inactive_level.61570424508022952146647703574260393848044575015199520703488806579759321447294
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10084220891 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcc79c210) == 0x0
  UVM_INFO @ 10084220891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.pattgen_inactive_level.32812801412462260193992155724746452450525804635099318760236715466177631756804
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10302137015 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x14d42850) == 0x0
  UVM_INFO @ 10302137015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```