PATTGEN Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 7.000s 136.103us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 19.534us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 12.198us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 298.087us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 44.550us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 3.000s 60.370us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 12.198us 20 20 100.00
pattgen_csr_aliasing 3.000s 44.550us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.750m 78.915ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.883m 10.956ms 50 50 100.00
V2 error pattgen_error 4.000s 16.673us 50 50 100.00
V2 stress_all pattgen_stress_all 2.867m 3.994ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 67.418us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 10.307us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 9.000s 179.683us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 9.000s 179.683us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 19.534us 5 5 100.00
pattgen_csr_rw 3.000s 12.198us 20 20 100.00
pattgen_csr_aliasing 3.000s 44.550us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 32.617us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 19.534us 5 5 100.00
pattgen_csr_rw 3.000s 12.198us 20 20 100.00
pattgen_csr_aliasing 3.000s 44.550us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 32.617us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 88.403us 20 20 100.00
pattgen_sec_cm 2.000s 124.186us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 88.403us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 30.833m 89.111ms 7 50 14.00
V3 TOTAL 7 50 14.00
Unmapped tests pattgen_inactive_level 1.600m 10.031ms 45 50 90.00
TOTAL 522 570 91.58

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results