PATTGEN Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	136.103us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	19.534us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	12.198us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	298.087us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	44.550us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	60.370us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	12.198us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.550us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.750m	78.915ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	10.956ms	50	50	100.00
V2	error	pattgen_error	4.000s	16.673us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.867m	3.994ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	67.418us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	10.307us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	179.683us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	179.683us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	19.534us	5	5	100.00
		pattgen_csr_rw	3.000s	12.198us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.550us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	32.617us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	19.534us	5	5	100.00
		pattgen_csr_rw	3.000s	12.198us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.550us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	32.617us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	88.403us	20	20	100.00
		pattgen_sec_cm	2.000s	124.186us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	88.403us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.833m	89.111ms	7	50	14.00
V3		TOTAL			7	50	14.00
	Unmapped tests	pattgen_inactive_level	1.600m	10.031ms	45	50	90.00
		TOTAL			522	570	91.58

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 37 failures:

Test pattgen_stress_all_with_rand_reset has 37 failures.

1.pattgen_stress_all_with_rand_reset.95440310327635263523256258691216486441309847160848679058384417479565430029508
Line 733, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 132305118573 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 132305167082 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 132305167082 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 6/10
  UVM_INFO @ 132305377610 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.79796438216029185411505604345962703671089548878319708453700838534860483360081
Line 1234, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 164628074847 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 164628089049 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 164628089049 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 164628393395 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 35 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 0.pattgen_stress_all_with_rand_reset.13055257174817737628458867263726200874298000788272562556770586684869196005750
    Line 314, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 527776351 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 18.pattgen_stress_all_with_rand_reset.82956557022076632727087048541643478660854320822871514564466624595544788026558
    Line 772, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25531995850 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 4 failures:
- Test pattgen_inactive_level has 4 failures.
  - 0.pattgen_inactive_level.110662571467926926233938190978769455853419737472079590742191293888566030625180
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10006145808 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x11b6cbd0) == 0x0
  UVM_INFO @ 10006145808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.pattgen_inactive_level.32372628373125388139514171358841357972009822071648497421890274199916573950071
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10035922036 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x51fb94d0) == 0x0
  UVM_INFO @ 10035922036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 20.pattgen_inactive_level.114139392581616613242256455644454093568418116773860348015954071770408479666023
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10004839268 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb697ac10) == 0x0
  UVM_INFO @ 10004839268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```