PATTGEN Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	11.000s	208.041us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	22.345us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	15.704us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	194.874us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	27.343us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	29.997us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	15.704us	20	20	100.00
		pattgen_csr_aliasing	2.000s	27.343us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.050m	10.621ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	4.538ms	50	50	100.00
V2	error	pattgen_error	3.000s	209.095us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.933m	3.954ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	48.258us	50	50	100.00
V2	intr_test	pattgen_intr_test	17.000s	10.524us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	255.393us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	255.393us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	22.345us	5	5	100.00
		pattgen_csr_rw	12.000s	15.704us	20	20	100.00
		pattgen_csr_aliasing	2.000s	27.343us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	26.737us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	22.345us	5	5	100.00
		pattgen_csr_rw	12.000s	15.704us	20	20	100.00
		pattgen_csr_aliasing	2.000s	27.343us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	26.737us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	50.301us	20	20	100.00
		pattgen_sec_cm	3.000s	57.934us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	50.301us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	41.283m	184.558ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	1.467m	10.011ms	48	50	96.00
		TOTAL			532	570	93.33

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:

Test pattgen_stress_all_with_rand_reset has 36 failures.

0.pattgen_stress_all_with_rand_reset.90797545767214833817004462482213525840880875264687746171637193633127398936823
Line 457, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3929932772 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3929942022 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3929942022 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 3930014185 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.6258349984570462875045130772799113271829254989208327473700492593536164403633
Line 506, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26753009128 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 26753014117 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 26753014117 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 26753218197 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 34 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 9.pattgen_inactive_level.107382608691113039970314185853983014012878138213283905439443076927308419098946
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10065255994 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x40749d10) == 0x0
  UVM_INFO @ 10065255994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 44.pattgen_inactive_level.37245336536564979961299498018646502514254920322749312025808919447765062100871
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010743530 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x22dea410) == 0x0
  UVM_INFO @ 10010743530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```