PATTGEN Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	18.000s	263.108us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	14.880us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	13.000s	33.392us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	14.000s	121.187us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	24.215us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	106.033us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	13.000s	33.392us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.215us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.717m	4.487ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.733m	10.962ms	50	50	100.00
V2	error	pattgen_error	7.000s	74.899us	49	50	98.00
V2	stress_all	pattgen_stress_all	1.800m	2.865ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	12.555us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	24.414us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	111.666us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	111.666us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	14.880us	5	5	100.00
		pattgen_csr_rw	13.000s	33.392us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.215us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	84.653us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	14.880us	5	5	100.00
		pattgen_csr_rw	13.000s	33.392us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.215us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	84.653us	20	20	100.00
V2		TOTAL			339	340	99.71
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	88.376us	20	20	100.00
		pattgen_sec_cm	3.000s	221.726us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	88.376us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	31.683m	260.422ms	17	50	34.00
V3		TOTAL			17	50	34.00
	Unmapped tests	pattgen_inactive_level	2.250m	10.038ms	47	50	94.00
		TOTAL			533	570	93.51

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	7	87.50
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 29 failures:

Test pattgen_stress_all_with_rand_reset has 29 failures.

0.pattgen_stress_all_with_rand_reset.106356536891342713673242693229901494953701142706351655622950646785237448746210
Line 771, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36523055373 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 36523062272 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 36523062272 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 36523254582 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.10605401392372270805476198843956523385713048951389940521004468066578706930237
Line 963, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28547181989 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 28547190089 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28547190089 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 28547220089 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 27 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 5.pattgen_stress_all_with_rand_reset.9211350806652082788979660815576469396846506138302636923499658001586420259262
    Line 568, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 71816955869 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 29.pattgen_stress_all_with_rand_reset.112371436954991574937545531219462091888346514128347744325805647620344060022889
    Line 1176, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57526639815 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 2.pattgen_inactive_level.26023438472858202666453938659905539403882255175444495144042602177288104860420
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10037764686 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4319bf50) == 0x0
  UVM_INFO @ 10037764686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.pattgen_inactive_level.46761480884499378300587563542213687150101556352823887602960513799270691874434
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10034867752 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc7a24e50) == 0x0
  UVM_INFO @ 10034867752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (pattgen_scoreboard.sv:249) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_error has 1 failures.
  - 8.pattgen_error.74272529140524971814621068427398208335601732915675341033260379788884817654704
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_error/latest/run.log
```
  UVM_ERROR @  69725304 ps: (pattgen_scoreboard.sv:249) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  -------------------------------------
  Name       Type          Size  Value
  -------------------------------------
  exp_item   pattgen_item  -     @10207
```