PATTGEN Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	5.000s	83.266us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	47.932us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	13.347us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.698ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	39.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	29.256us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	13.347us	20	20	100.00
		pattgen_csr_aliasing	3.000s	39.262us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.050m	1.392ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.817m	18.079ms	50	50	100.00
V2	error	pattgen_error	4.000s	142.939us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.750m	11.118ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	143.939us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	13.558us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	12.000s	39.925us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	12.000s	39.925us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	47.932us	5	5	100.00
		pattgen_csr_rw	12.000s	13.347us	20	20	100.00
		pattgen_csr_aliasing	3.000s	39.262us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	54.450us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	47.932us	5	5	100.00
		pattgen_csr_rw	12.000s	13.347us	20	20	100.00
		pattgen_csr_aliasing	3.000s	39.262us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	54.450us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	12.000s	88.974us	20	20	100.00
		pattgen_sec_cm	3.000s	61.770us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	12.000s	88.974us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	35.350m	200.575ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	1.583m	10.005ms	49	50	98.00
		TOTAL			534	570	93.68

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

0.pattgen_stress_all_with_rand_reset.106403552663503674611606452612115755606617523121642892411329215034515094331610
Line 387, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6926352375 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 6926354849 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6926354849 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 6926386100 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.75172464983932493259164558708864922073567906196477544535137944012083952497460
Line 706, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 54249584629 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 54249610824 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 54249610824 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 54249777492 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 2.pattgen_stress_all_with_rand_reset.3168844354448826121472037705578312787150692143733892544755655285560765357726
    Line 513, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12865250314 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 39.pattgen_stress_all_with_rand_reset.61424785540207925176937147365933687717996050985043218672186756502126525715354
    Line 624, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31957194059 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 30.pattgen_inactive_level.7356911939346602664608798598648052473875628006606820404295015724077221860182
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10005150488 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8a4ad910) == 0x0
  UVM_INFO @ 10005150488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```