PATTGEN Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	113.687us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	72.217us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	8.000s	22.712us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	142.681us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	16.208us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	31.011us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	8.000s	22.712us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.208us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.767m	78.911ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	10.526ms	50	50	100.00
V2	error	pattgen_error	13.000s	16.166us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.533m	60.415ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	35.226us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	15.465us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	338.187us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	338.187us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	72.217us	5	5	100.00
		pattgen_csr_rw	8.000s	22.712us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.208us	5	5	100.00
		pattgen_same_csr_outstanding	13.000s	24.842us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	72.217us	5	5	100.00
		pattgen_csr_rw	8.000s	22.712us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.208us	5	5	100.00
		pattgen_same_csr_outstanding	13.000s	24.842us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	49.353us	20	20	100.00
		pattgen_sec_cm	2.000s	141.885us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	49.353us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.050m	74.446ms	11	50	22.00
V3		TOTAL			11	50	22.00
	Unmapped tests	pattgen_inactive_level	1.983m	10.031ms	47	50	94.00
		TOTAL			528	570	92.63

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

0.pattgen_stress_all_with_rand_reset.66401304007558189943692475899495506684796354671633053009572945933331589224064
Line 381, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8902337158 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8902353527 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8902353527 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 8902433527 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.76303330199724073230823940146946109429642213349170323168620965078128643849563
Line 409, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36344066606 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 36344076622 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 36344076622 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 36344436622 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 8.pattgen_stress_all_with_rand_reset.109677230142017349680658133642817890048051853555343877265917376136175367316361
    Line 583, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 66014047449 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 22.pattgen_stress_all_with_rand_reset.16088903324958750596608892744486187882332258799111170898995183252247264792481
    Line 605, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23823143694 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 7.pattgen_inactive_level.20225682509164219750394909251627136501576466037434163556025538983855339180126
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008791329 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x6e57f50) == 0x0
  UVM_INFO @ 10008791329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.pattgen_inactive_level.94470741425957101882859147214001571764052006258123959221435383955903500515545
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010507048 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x4ab2c810) == 0x0
  UVM_INFO @ 10010507048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.