PATTGEN Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	6.000s	102.342us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	45.627us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	16.695us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	292.732us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	33.005us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	30.346us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	16.695us	20	20	100.00
		pattgen_csr_aliasing	3.000s	33.005us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.767m	21.924ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.967m	2.894ms	50	50	100.00
V2	error	pattgen_error	3.000s	57.731us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.050m	36.126ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	49.906us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	23.598us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	689.921us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	689.921us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	45.627us	5	5	100.00
		pattgen_csr_rw	3.000s	16.695us	20	20	100.00
		pattgen_csr_aliasing	3.000s	33.005us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	69.489us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	45.627us	5	5	100.00
		pattgen_csr_rw	3.000s	16.695us	20	20	100.00
		pattgen_csr_aliasing	3.000s	33.005us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	69.489us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	192.567us	20	20	100.00
		pattgen_sec_cm	3.000s	153.409us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	192.567us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	35.650m	337.658ms	19	50	38.00
V3		TOTAL			19	50	38.00
	Unmapped tests	pattgen_inactive_level	1.433m	10.014ms	46	50	92.00
		TOTAL			535	570	93.86

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 25 failures:

Test pattgen_stress_all_with_rand_reset has 25 failures.

6.pattgen_stress_all_with_rand_reset.70219574422652798029098745361305885831658052622927917556085730666627666994635
Line 498, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19722132765 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 19722137677 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 19722137677 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 19722262675 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

10.pattgen_stress_all_with_rand_reset.66012104566239709700525120727955496144685604271295717045333579960228395815947
Line 583, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16671416129 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 16671422382 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16671422382 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 16671503190 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 23 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 4.pattgen_stress_all_with_rand_reset.822249738416050056245343487748421981538815943848232026132778016675968520383
    Line 561, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83583983649 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 7.pattgen_stress_all_with_rand_reset.105613192159708021377833385687874778353664644313586831362965790360859720331658
    Line 309, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1003368283 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 0.pattgen_inactive_level.110665575246484746955200256394743033245510209633025582599660843685768053354240
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008463800 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdbfaa290) == 0x0
  UVM_INFO @ 10008463800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.pattgen_inactive_level.85637218189564219777366371504967001836435883975614856765454336553392908024644
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10056613610 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x63707350) == 0x0
  UVM_INFO @ 10056613610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 38.pattgen_inactive_level.114379288356226803949105529733241627177922086013586430079279809996098655829923
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10014206889 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x92e69c90) == 0x0
  UVM_INFO @ 10014206889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```