PATTGEN Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	5.000s	686.313us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	12.402us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	32.614us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.216ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	19.456us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	298.847us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	32.614us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.456us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.750m	15.772ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.950m	2.635ms	50	50	100.00
V2	error	pattgen_error	3.000s	15.520us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.967m	7.806ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	22.411us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	16.144us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	92.843us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	92.843us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	12.402us	5	5	100.00
		pattgen_csr_rw	3.000s	32.614us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.456us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	97.495us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	12.402us	5	5	100.00
		pattgen_csr_rw	3.000s	32.614us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.456us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	97.495us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	168.565us	20	20	100.00
		pattgen_sec_cm	2.000s	59.617us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	168.565us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	43.433m	224.944ms	9	50	18.00
V3		TOTAL			9	50	18.00
	Unmapped tests	pattgen_inactive_level	9.000s	372.252us	50	50	100.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 39 failures:

Test pattgen_stress_all_with_rand_reset has 39 failures.

1.pattgen_stress_all_with_rand_reset.23896951590440356750043133947520576983806460317474415082184390803024646382031
Line 574, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 85939127839 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 85939160126 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 85939160126 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 85939588700 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.28306246795519463421921204576764519718495022145915491940043403906284323472254
Line 618, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 82054455701 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 82054478022 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 82054478022 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 82054638022 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 37 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 3.pattgen_stress_all_with_rand_reset.67791950833093391516995751937864097309602625441583340431121793746006779254417
    Line 432, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28123067205 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 44.pattgen_stress_all_with_rand_reset.34198296160808517636645672823093168596121876429267162669788737956879376405095
    Line 896, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31636945728 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```