PATTGEN Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	178.247us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	44.142us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	35.172us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	370.715us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	174.731us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	30.466us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	35.172us	20	20	100.00
		pattgen_csr_aliasing	3.000s	174.731us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.867m	8.218ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	10.519ms	50	50	100.00
V2	error	pattgen_error	12.000s	29.615us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.900m	5.337ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	22.662us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	13.986us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	234.047us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	234.047us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	44.142us	5	5	100.00
		pattgen_csr_rw	3.000s	35.172us	20	20	100.00
		pattgen_csr_aliasing	3.000s	174.731us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	54.827us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	44.142us	5	5	100.00
		pattgen_csr_rw	3.000s	35.172us	20	20	100.00
		pattgen_csr_aliasing	3.000s	174.731us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	54.827us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	311.101us	20	20	100.00
		pattgen_sec_cm	3.000s	36.144us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	311.101us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	52.167m	140.074ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	5.867m	10.002ms	44	50	88.00
		TOTAL			528	570	92.63

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.91	100.00	100.00	100.00	99.16	96.13	--	100.00	90.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.47823731090969808970619363338917125911856658425059063480089553980183877282884
Line 443, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38459489074 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 38459511161 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 38459511161 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 38459802830 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.103048591200639287780495325610864438170341171945315501312651485807285552813248
Line 577, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15536119962 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 15536123817 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15536123817 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 6/10
  UVM_INFO @ 15536196987 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 8.pattgen_stress_all_with_rand_reset.73768006859220019242989913411660956293587383480736615329682610889404071781447
    Line 1160, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 90162086467 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 11.pattgen_stress_all_with_rand_reset.17178883582649059880855894932857519545624133900723030806883734858330452954361
    Line 872, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47989552472 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 4 failures:
- Test pattgen_inactive_level has 4 failures.
  - 1.pattgen_inactive_level.105395401147887591866327347837597311400353575539621461375537541123133017891928
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10030382598 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8055fe90) == 0x0
  UVM_INFO @ 10030382598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.pattgen_inactive_level.34813793282079854133682761181993248002291373976887698057344010487619511438670
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10002226960 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x170e48d0) == 0x0
  UVM_INFO @ 10002226960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 36.pattgen_inactive_level.28462450094466159709306362483195701195021476302480119308472729400768042774114
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10393514115 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3b3a0990) == 0x0
  UVM_INFO @ 10393514115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.pattgen_inactive_level.43854967952261553666204622007184504355347115293243635412578182041885728511877
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10024439698 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe2c6abd0) == 0x0
  UVM_INFO @ 10024439698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```