PATTGEN Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	38.043us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	26.922us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	59.789us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	301.324us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	19.946us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	27.308us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	59.789us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.946us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	5.529ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	5.486ms	50	50	100.00
V2	error	pattgen_error	7.000s	17.384us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.933m	16.650ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	14.893us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	44.305us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	137.034us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	137.034us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	26.922us	5	5	100.00
		pattgen_csr_rw	3.000s	59.789us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.946us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	48.430us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	26.922us	5	5	100.00
		pattgen_csr_rw	3.000s	59.789us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.946us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	48.430us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	317.404us	20	20	100.00
		pattgen_sec_cm	3.000s	212.790us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	317.404us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	38.417m	422.167ms	24	50	48.00
V3		TOTAL			24	50	48.00
	Unmapped tests	pattgen_inactive_level	5.583m	10.041ms	44	50	88.00
		TOTAL			538	570	94.39

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 23 failures:

Test pattgen_stress_all_with_rand_reset has 23 failures.

2.pattgen_stress_all_with_rand_reset.57973154751712569217551423300005045514418707474573644508911789715970285649761
Line 1097, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 51630437829 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 51630447579 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 51630447579 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 51630508185 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

5.pattgen_stress_all_with_rand_reset.113543267604935624293107150159630580064907157509907013361095127536048273750332
Line 470, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8808174229 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8808176826 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8808176826 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 8808261034 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 21 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 5 failures:
- Test pattgen_inactive_level has 5 failures.
  - 0.pattgen_inactive_level.103712114300786676867371905895915801795840729734595794196302409166974001397925
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10016880522 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1989a10) == 0x0
  UVM_INFO @ 10016880522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.pattgen_inactive_level.64531087353058906124966090600986039942702837505903528556979487844190323861270
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10100512315 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdf1da150) == 0x0
  UVM_INFO @ 10100512315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 6.pattgen_stress_all_with_rand_reset.6794145550238507555275146349139797014270963963030168859334594418920029651961
    Line 391, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21499922452 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 22.pattgen_stress_all_with_rand_reset.100251765216075932744556765292717014157236531559835429779985655883415390052169
    Line 518, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43454385614 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 44.pattgen_inactive_level.265090097408632907316126231066194017187040117277290262482031808892405813111
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10085907418 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x820b4dd0) == 0x0
  UVM_INFO @ 10085907418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```