PATTGEN Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	537.641us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	8.000s	27.061us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	24.257us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	193.863us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	44.439us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	13.000s	56.035us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	24.257us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.439us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.967m	11.058ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	2.689ms	50	50	100.00
V2	error	pattgen_error	8.000s	38.292us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.817m	9.853ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	12.355us	50	50	100.00
V2	intr_test	pattgen_intr_test	9.000s	120.079us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	14.000s	411.097us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	14.000s	411.097us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	8.000s	27.061us	5	5	100.00
		pattgen_csr_rw	7.000s	24.257us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.439us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	18.635us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	8.000s	27.061us	5	5	100.00
		pattgen_csr_rw	7.000s	24.257us	20	20	100.00
		pattgen_csr_aliasing	3.000s	44.439us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	18.635us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	12.000s	169.039us	20	20	100.00
		pattgen_sec_cm	2.000s	124.199us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	12.000s	169.039us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	39.567m	637.794ms	16	50	32.00
V3		TOTAL			16	50	32.00
	Unmapped tests	pattgen_inactive_level	5.667m	10.003ms	47	50	94.00
		TOTAL			533	570	93.51

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

4.pattgen_stress_all_with_rand_reset.91036986630975450983853689365815705455521268057293128139311732841321031607698
Line 489, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31412261037 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 31412273445 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 31412273445 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 31412593445 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

5.pattgen_stress_all_with_rand_reset.75913380409448437431380435539696334938673801856946759654201141191389240372968
Line 319, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3350216232 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3350222646 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3350222646 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 3350597646 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 2.pattgen_inactive_level.49937932562096796629443999668566612042311153468674179925145748461238376794734
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10019948878 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb9f4e6d0) == 0x0
  UVM_INFO @ 10019948878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.pattgen_inactive_level.21057219781691948221783816927402661300814755826690111880515788165953407862309
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10002723567 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbe8425d0) == 0x0
  UVM_INFO @ 10002723567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 14.pattgen_stress_all_with_rand_reset.95043214354492374962201060992923501052616730279805054999632297443313989604597
    Line 532, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37879556213 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 16.pattgen_stress_all_with_rand_reset.37732916780541675900206586064765731112033875341814889226488461130145612880846
    Line 398, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 113889306387 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.