PATTGEN Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 8.000s 327.236us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 2.000s 14.982us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 15.653us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 9.000s 926.333us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 14.718us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 8.000s 18.318us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 15.653us 20 20 100.00
pattgen_csr_aliasing 3.000s 14.718us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.750m 16.431ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.950m 5.482ms 50 50 100.00
V2 error pattgen_error 8.000s 47.004us 50 50 100.00
V2 stress_all pattgen_stress_all 2.650m 19.842ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 23.626us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 13.935us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 518.090us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 518.090us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 2.000s 14.982us 5 5 100.00
pattgen_csr_rw 3.000s 15.653us 20 20 100.00
pattgen_csr_aliasing 3.000s 14.718us 5 5 100.00
pattgen_same_csr_outstanding 17.000s 16.407us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 2.000s 14.982us 5 5 100.00
pattgen_csr_rw 3.000s 15.653us 20 20 100.00
pattgen_csr_aliasing 3.000s 14.718us 5 5 100.00
pattgen_same_csr_outstanding 17.000s 16.407us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 8.000s 84.404us 20 20 100.00
pattgen_sec_cm 3.000s 122.036us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 8.000s 84.404us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 38.667m 462.327ms 15 50 30.00
V3 TOTAL 15 50 30.00
Unmapped tests pattgen_inactive_level 1.417m 10.027ms 45 50 90.00
TOTAL 530 570 92.98

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results