PATTGEN Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	327.236us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	14.982us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	15.653us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	9.000s	926.333us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	14.718us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	18.318us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	15.653us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.718us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.750m	16.431ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.950m	5.482ms	50	50	100.00
V2	error	pattgen_error	8.000s	47.004us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.650m	19.842ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	23.626us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	13.935us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	518.090us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	518.090us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	14.982us	5	5	100.00
		pattgen_csr_rw	3.000s	15.653us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.718us	5	5	100.00
		pattgen_same_csr_outstanding	17.000s	16.407us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	14.982us	5	5	100.00
		pattgen_csr_rw	3.000s	15.653us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.718us	5	5	100.00
		pattgen_same_csr_outstanding	17.000s	16.407us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	84.404us	20	20	100.00
		pattgen_sec_cm	3.000s	122.036us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	84.404us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	38.667m	462.327ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	1.417m	10.027ms	45	50	90.00
		TOTAL			530	570	92.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.34631204218137240540212424486613661725261869151203838695553549705425924190363
Line 1086, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 162359629744 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 162359667272 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 162359667272 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 6/10
  UVM_INFO @ 162359947272 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.2591521556005238399086147196884815433683106620441623494333361069579865855471
Line 369, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31749246612 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 31749276549 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 31749276549 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 31749409883 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 15.pattgen_stress_all_with_rand_reset.2675198334181106864143407859929529659710574667497158423425824753086893410232
    Line 635, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17001301498 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 19.pattgen_stress_all_with_rand_reset.115636293309022825463350134735623077547080004279974094342084371333795150304042
    Line 472, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25803157363 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 33.pattgen_inactive_level.87493567769498797321405411192925155277031380067806625837957248292159286511529
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10148784415 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6e273fd0) == 0x0
  UVM_INFO @ 10148784415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.pattgen_inactive_level.63571953290776518792435380480904991585811050086435962576539291228494656405239
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10032746345 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x965d5690) == 0x0
  UVM_INFO @ 10032746345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 1.pattgen_inactive_level.111828261967703649645808023722273065834276904255068825784690849253492795455774
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10151013315 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3623d750) == 0x0
  UVM_INFO @ 10151013315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.pattgen_inactive_level.106872400252157379716947254760173615053810036272167637196553277270206389779126
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10021362346 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6817a4d0) == 0x0
  UVM_INFO @ 10021362346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```