PATTGEN Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	918.535us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	25.875us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	23.525us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	19.000s	463.638us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	32.843us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	19.210us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	23.525us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.843us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.950m	43.850ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.583m	4.883ms	50	50	100.00
V2	error	pattgen_error	12.000s	99.744us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.117m	2.757ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	11.752us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	16.809us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	14.000s	362.584us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	14.000s	362.584us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	25.875us	5	5	100.00
		pattgen_csr_rw	7.000s	23.525us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.843us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	26.443us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	25.875us	5	5	100.00
		pattgen_csr_rw	7.000s	23.525us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.843us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	26.443us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	13.000s	78.740us	20	20	100.00
		pattgen_sec_cm	2.000s	175.015us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	13.000s	78.740us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	23.583m	389.081ms	16	50	32.00
V3		TOTAL			16	50	32.00
	Unmapped tests	pattgen_inactive_level	1.000m	10.030ms	44	50	88.00
		TOTAL			530	570	92.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 29 failures:

Test pattgen_stress_all_with_rand_reset has 29 failures.

2.pattgen_stress_all_with_rand_reset.97441231316912442184952199178183101176628823499424035971475433960323903377544
Line 985, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 148718590818 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 148718602968 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 148718602968 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 148718842968 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.108888024751405966729713325063882285967513569599679286050697301450568321449400
Line 407, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13434581012 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 13434600612 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13434600612 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 13434743468 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 27 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 6 failures:
- Test pattgen_inactive_level has 6 failures.
  - 8.pattgen_inactive_level.84275338925095268633771021652622378696374601230083018273681960268799308303872
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10052284605 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x11757dd0) == 0x0
  UVM_INFO @ 10052284605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.pattgen_inactive_level.109899359738632287641977333659435115928503053308264229597511602041044453979754
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10029776295 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4e5865d0) == 0x0
  UVM_INFO @ 10029776295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 1.pattgen_stress_all_with_rand_reset.90995338611111828927056346695687020610632490865211802674980552339213088547369
    Line 298, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 380296347 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 17.pattgen_stress_all_with_rand_reset.45737615781407320919020813305945977324121465575640226157094179460885164947868
    Line 873, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 224852090241 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.