PATTGEN Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	647.998us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	15.787us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	20.008us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	259.043us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	103.041us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	31.288us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	20.008us	20	20	100.00
		pattgen_csr_aliasing	3.000s	103.041us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.867m	16.432ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	5.263ms	50	50	100.00
V2	error	pattgen_error	3.000s	17.035us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.017m	2.767ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	13.399us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	14.019us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	107.661us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	107.661us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	15.787us	5	5	100.00
		pattgen_csr_rw	3.000s	20.008us	20	20	100.00
		pattgen_csr_aliasing	3.000s	103.041us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	146.543us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	15.787us	5	5	100.00
		pattgen_csr_rw	3.000s	20.008us	20	20	100.00
		pattgen_csr_aliasing	3.000s	103.041us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	146.543us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	290.459us	20	20	100.00
		pattgen_sec_cm	2.000s	176.803us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	290.459us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	52.050m	540.694ms	13	50	26.00
V3		TOTAL			13	50	26.00
	Unmapped tests	pattgen_inactive_level	31.000s	10.113ms	48	50	96.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

1.pattgen_stress_all_with_rand_reset.111332599426387170633870941531122994103436821998854640168025625503653414309516
Line 312, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 932721634 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 932730771 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 932730771 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 932762022 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.16518086095331448057177768918148073480176238823975775778726645223887311911930
Line 1385, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 329891824825 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 329891836369 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 329891836369 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 329892044704 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 2.pattgen_stress_all_with_rand_reset.69754027351421731471419180636296290937929260426159755693152273706533846716298
    Line 307, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 385311327 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 34.pattgen_stress_all_with_rand_reset.63452636564369624733367548517083530556849181820486982081933143831354928991426
    Line 384, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9869377577 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 25.pattgen_inactive_level.32690658330299485795547654334379342106840365471185864934376692510889191795328
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10327703859 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbc42550) == 0x0
  UVM_INFO @ 10327703859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.pattgen_inactive_level.26284690773026462853236925596484442214439185002586935364412000956799509640963
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10112882046 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc1c56590) == 0x0
  UVM_INFO @ 10112882046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```