PATTGEN Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	133.092us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	60.978us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	28.333us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	930.894us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	32.086us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	196.245us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	28.333us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.086us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.933m	4.575ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.417m	12.097ms	50	50	100.00
V2	error	pattgen_error	3.000s	14.911us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.717m	9.529ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	40.388us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	17.484us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	322.845us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	322.845us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	60.978us	5	5	100.00
		pattgen_csr_rw	3.000s	28.333us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.086us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	61.367us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	60.978us	5	5	100.00
		pattgen_csr_rw	3.000s	28.333us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.086us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	61.367us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	181.738us	20	20	100.00
		pattgen_sec_cm	2.000s	68.079us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	181.738us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	38.033m	94.865ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	2.817m	10.032ms	48	50	96.00
		TOTAL			533	570	93.51

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.78454488736757206647706895668538567978662624277006128328800767590097333466330
Line 587, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19294839483 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 19294844125 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 19294844125 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 19294864959 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.82505989127103692133255629031121362086083162119209118144671256371889534855075
Line 526, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8333088276 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8333098455 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8333098455 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 8333161611 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 18.pattgen_stress_all_with_rand_reset.67862495801605085845599785885014446269633522856919639104091431954536023284328
    Line 298, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 731973018 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 26.pattgen_stress_all_with_rand_reset.31077153550686784037402569633802766278584457544012114210443211848030222788541
    Line 746, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30830118575 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 10.pattgen_inactive_level.98860253551153803587075279915456682116797968932815982975964466488547799496571
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10011595384 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xfcf72ad0) == 0x0
  UVM_INFO @ 10011595384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.pattgen_inactive_level.10498190493494698564206630598787856944463092696223367606836010580259853330844
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10032203080 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9eb9fa90) == 0x0
  UVM_INFO @ 10032203080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```