PATTGEN Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 11.000s 911.142us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 36.917us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 15.642us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 4.000s 41.394us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 29.123us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 4.000s 31.026us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 15.642us 20 20 100.00
pattgen_csr_aliasing 3.000s 29.123us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.000m 2.795ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.767m 2.632ms 50 50 100.00
V2 error pattgen_error 3.000s 66.539us 50 50 100.00
V2 stress_all pattgen_stress_all 2.800m 15.907ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 115.418us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 28.718us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 416.779us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 416.779us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 36.917us 5 5 100.00
pattgen_csr_rw 3.000s 15.642us 20 20 100.00
pattgen_csr_aliasing 3.000s 29.123us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 27.289us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 36.917us 5 5 100.00
pattgen_csr_rw 3.000s 15.642us 20 20 100.00
pattgen_csr_aliasing 3.000s 29.123us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 27.289us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 3.000s 84.125us 20 20 100.00
pattgen_sec_cm 3.000s 93.224us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 3.000s 84.125us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 42.483m 396.917ms 16 50 32.00
V3 TOTAL 16 50 32.00
Unmapped tests pattgen_inactive_level 5.800m 10.012ms 45 50 90.00
TOTAL 531 570 93.16

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results