PATTGEN Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	11.000s	911.142us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	36.917us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	15.642us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	41.394us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	29.123us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	31.026us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	15.642us	20	20	100.00
		pattgen_csr_aliasing	3.000s	29.123us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.000m	2.795ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.767m	2.632ms	50	50	100.00
V2	error	pattgen_error	3.000s	66.539us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.800m	15.907ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	115.418us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	28.718us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	416.779us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	416.779us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	36.917us	5	5	100.00
		pattgen_csr_rw	3.000s	15.642us	20	20	100.00
		pattgen_csr_aliasing	3.000s	29.123us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	27.289us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	36.917us	5	5	100.00
		pattgen_csr_rw	3.000s	15.642us	20	20	100.00
		pattgen_csr_aliasing	3.000s	29.123us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	27.289us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	84.125us	20	20	100.00
		pattgen_sec_cm	3.000s	93.224us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	84.125us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	42.483m	396.917ms	16	50	32.00
V3		TOTAL			16	50	32.00
	Unmapped tests	pattgen_inactive_level	5.800m	10.012ms	45	50	90.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.11310225066992518678679667832048092466251848059247494695210205508672414139496
Line 498, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7028523516 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 7028531322 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7028531322 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 7028631322 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.10282756327683954632285840737105771184811749182882450920986045958167740530334
Line 396, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6144702107 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 6144711327 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6144711327 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 6144836328 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 5 failures:
- Test pattgen_inactive_level has 5 failures.
  - 2.pattgen_inactive_level.29402551676988036183813060083335961543029969300590504200060227213558588863668
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10014924173 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x31bc51d0) == 0x0
  UVM_INFO @ 10014924173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.pattgen_inactive_level.28945908834438717558317365163903648558551514827141807539901125017007011030305
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10397854939 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xae116210) == 0x0
  UVM_INFO @ 10397854939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 7.pattgen_stress_all_with_rand_reset.28927565917453996068598824279432977203675146699374572719216334231672524374541
    Line 490, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11550399616 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 18.pattgen_stress_all_with_rand_reset.113860104463641449629708799457709306271801938698435216110790291818228089333947
    Line 484, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8095398596 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```