PATTGEN Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 10.000s 211.727us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 44.000us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 16.774us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 4.000s 241.370us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 57.156us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 3.000s 51.844us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 16.774us 20 20 100.00
pattgen_csr_aliasing 3.000s 57.156us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 1.900m 43.893ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.567m 2.187ms 50 50 100.00
V2 error pattgen_error 3.000s 36.776us 50 50 100.00
V2 stress_all pattgen_stress_all 1.950m 14.960ms 50 50 100.00
V2 alert_test pattgen_alert_test 2.000s 47.923us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 31.606us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 47.464us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 47.464us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 44.000us 5 5 100.00
pattgen_csr_rw 3.000s 16.774us 20 20 100.00
pattgen_csr_aliasing 3.000s 57.156us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 17.794us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 44.000us 5 5 100.00
pattgen_csr_rw 3.000s 16.774us 20 20 100.00
pattgen_csr_aliasing 3.000s 57.156us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 17.794us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 161.625us 20 20 100.00
pattgen_sec_cm 2.000s 116.497us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 161.625us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 34.400m 250.760ms 22 50 44.00
V3 TOTAL 22 50 44.00
Unmapped tests pattgen_inactive_level 2.933m 10.004ms 47 50 94.00
TOTAL 539 570 94.56

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results