PATTGEN Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	211.727us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	44.000us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	16.774us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	241.370us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	57.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	51.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	16.774us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.156us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.900m	43.893ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.567m	2.187ms	50	50	100.00
V2	error	pattgen_error	3.000s	36.776us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.950m	14.960ms	50	50	100.00
V2	alert_test	pattgen_alert_test	2.000s	47.923us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	31.606us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	47.464us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	47.464us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	44.000us	5	5	100.00
		pattgen_csr_rw	3.000s	16.774us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.156us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	17.794us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	44.000us	5	5	100.00
		pattgen_csr_rw	3.000s	16.774us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.156us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	17.794us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	161.625us	20	20	100.00
		pattgen_sec_cm	2.000s	116.497us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	161.625us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	34.400m	250.760ms	22	50	44.00
V3		TOTAL			22	50	44.00
	Unmapped tests	pattgen_inactive_level	2.933m	10.004ms	47	50	94.00
		TOTAL			539	570	94.56

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 28 failures:

Test pattgen_stress_all_with_rand_reset has 28 failures.

0.pattgen_stress_all_with_rand_reset.77613400154171211116111658603932336201940333101541164892648217668700202461202
Line 1289, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 50348215986 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 50348220976 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 50348220976 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 50348312812 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.88187578186894482067959491665942429568017589714333235064322545598660663799738
Line 497, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20148708673 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 20148716066 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 20148716066 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 20148763685 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 26 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 2.pattgen_inactive_level.13653967891116558074086166928713826738587511275673321737312557894492610287965
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10045200607 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xabba5ed0) == 0x0
  UVM_INFO @ 10045200607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.pattgen_inactive_level.39579790933976146669981155977697947840542825552034980730780843867873442136200
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008292456 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xf9026a50) == 0x0
  UVM_INFO @ 10008292456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.