PATTGEN Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	165.968us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	15.333us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	19.645us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	247.127us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	108.450us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	108.231us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	19.645us	20	20	100.00
		pattgen_csr_aliasing	3.000s	108.450us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.833m	35.848ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.133m	1.684ms	50	50	100.00
V2	error	pattgen_error	3.000s	49.860us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.867m	16.956ms	50	50	100.00
V2	alert_test	pattgen_alert_test	2.000s	15.392us	50	50	100.00
V2	intr_test	pattgen_intr_test	2.000s	51.077us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	164.981us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	164.981us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	15.333us	5	5	100.00
		pattgen_csr_rw	2.000s	19.645us	20	20	100.00
		pattgen_csr_aliasing	3.000s	108.450us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	93.721us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	15.333us	5	5	100.00
		pattgen_csr_rw	2.000s	19.645us	20	20	100.00
		pattgen_csr_aliasing	3.000s	108.450us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	93.721us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	125.734us	20	20	100.00
		pattgen_sec_cm	3.000s	103.847us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	125.734us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	28.883m	2.347s	20	50	40.00
V3		TOTAL			20	50	40.00
	Unmapped tests	pattgen_inactive_level	1.033m	10.488ms	46	50	92.00
		TOTAL			536	570	94.04

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.91	100.00	100.00	100.00	99.16	96.13	--	100.00	90.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

Test pattgen_stress_all_with_rand_reset has 28 failures.

0.pattgen_stress_all_with_rand_reset.43391361660329430066964592109034711321992566151352810954414924072100495974082
Line 443, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8374565416 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8374570693 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8374570693 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 8374663474 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.107754881290368164139512913553687243569510540211748620897361709295653179862287
Line 370, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2450732156 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2450732894 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2450732894 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 2450814526 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 26 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 7.pattgen_inactive_level.85019895056816598242488420521963113577092350331019141087363955811682772455312
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10028601181 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xabd44a90) == 0x0
  UVM_INFO @ 10028601181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.pattgen_inactive_level.53011476868826630650093271859760627553112708296938582993898866555591408388772
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10487682817 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x340c9610) == 0x0
  UVM_INFO @ 10487682817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 14.pattgen_stress_all_with_rand_reset.107906339548742306293837092780485456973274607637720318398995571007371416267823
    Line 409, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11283357174 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 35.pattgen_stress_all_with_rand_reset.66755215945660055095594849909434662202411256667999089030487386201713264135070
    Line 694, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131058806997 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 45.pattgen_inactive_level.36298701444862581875009864708432827423680789357757694903663019110118595269599
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10111237587 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1b7f2950) == 0x0
  UVM_INFO @ 10111237587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```