PATTGEN Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	126.930us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	154.276us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	26.128us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	354.922us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	50.355us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	26.878us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	26.128us	20	20	100.00
		pattgen_csr_aliasing	2.000s	50.355us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.817m	7.890ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	10.528ms	50	50	100.00
V2	error	pattgen_error	7.000s	14.585us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.533m	10.645ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	13.323us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	21.510us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	42.961us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	42.961us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	154.276us	5	5	100.00
		pattgen_csr_rw	3.000s	26.128us	20	20	100.00
		pattgen_csr_aliasing	2.000s	50.355us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	142.515us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	154.276us	5	5	100.00
		pattgen_csr_rw	3.000s	26.128us	20	20	100.00
		pattgen_csr_aliasing	2.000s	50.355us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	142.515us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	790.204us	20	20	100.00
		pattgen_sec_cm	3.000s	410.398us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	790.204us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	49.650m	135.125ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	1.867m	10.007ms	46	50	92.00
		TOTAL			530	570	92.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

1.pattgen_stress_all_with_rand_reset.92193084386177892520707396999489030167559769933271288417198743546970587698685
Line 530, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 49735344448 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 49735357794 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 49735357794 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 49735505942 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.15168708813882345285684128159322442237892193748265422951641418927574405314368
Line 660, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 99568478794 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 99568492024 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 99568492024 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 99568592023 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 8.pattgen_inactive_level.88874388710193174698906002135032454582783837231949504480819160594251871683830
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015634907 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x968af050) == 0x0
  UVM_INFO @ 10015634907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.pattgen_inactive_level.65419992057737889005710815156060191318475649715579760140042441723081675681073
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10006528448 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x60c4ed0) == 0x0
  UVM_INFO @ 10006528448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 16.pattgen_stress_all_with_rand_reset.76780775882536310115139887923054218298799672837406298842847649264139195849975
    Line 298, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 666078082 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 37.pattgen_stress_all_with_rand_reset.107269004193277468287449218193867208908096477037595194405780876850224174466778
    Line 314, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 733018181 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 26.pattgen_inactive_level.37837153939546517469189058277638183980032886275774709815910474126851450591419
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10048540937 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfe8b3fd0) == 0x0
  UVM_INFO @ 10048540937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.pattgen_inactive_level.40546250698871723534906809560836878927352268543429327909063012841012733119329
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008372461 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdf42bdd0) == 0x0
  UVM_INFO @ 10008372461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```