PATTGEN Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	160.728us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	20.580us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	14.577us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	255.316us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	5.000s	86.007us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	25.637us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	14.577us	20	20	100.00
		pattgen_csr_aliasing	5.000s	86.007us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.000m	2.637ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	52.588ms	50	50	100.00
V2	error	pattgen_error	15.000s	51.146us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.867m	11.017ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	28.354us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	14.923us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	402.096us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	402.096us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	20.580us	5	5	100.00
		pattgen_csr_rw	4.000s	14.577us	20	20	100.00
		pattgen_csr_aliasing	5.000s	86.007us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	30.962us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	20.580us	5	5	100.00
		pattgen_csr_rw	4.000s	14.577us	20	20	100.00
		pattgen_csr_aliasing	5.000s	86.007us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	30.962us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	303.354us	20	20	100.00
		pattgen_sec_cm	7.000s	37.123us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	303.354us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	43.983m	90.132ms	13	50	26.00
V3		TOTAL			13	50	26.00
	Unmapped tests	pattgen_inactive_level	1.383m	10.018ms	48	50	96.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:

Test pattgen_stress_all_with_rand_reset has 35 failures.

0.pattgen_stress_all_with_rand_reset.107067068331416538905218229263161429583741396074359033376122733902625645319448
Line 832, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 416138227210 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 416138370261 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 416138370261 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 416139203596 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.33833458605512576404575755537581008814979890625386706575121931989170048704176
Line 306, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3800678859 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3800693561 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3800693561 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 3800933561 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 33 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 13.pattgen_stress_all_with_rand_reset.53273036486082563299688629124097700446855044965234323385684832181529635233116
    Line 973, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39449870460 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 35.pattgen_stress_all_with_rand_reset.62561022309896343343789787037777419442181947036063189565744918308924308218811
    Line 769, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 440384537565 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 19.pattgen_inactive_level.15120634530624322684842628389057008392718984570448467931382553752925914393891
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10062400000 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x907b8950) == 0x0
  UVM_INFO @ 10062400000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.pattgen_inactive_level.105839243716762618235123090462157812867837511311868464910101737236977797203107
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10018161364 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7fad5150) == 0x0
  UVM_INFO @ 10018161364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```