PATTGEN Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	5.000s	94.171us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	17.079us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	44.276us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	512.555us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	45.337us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	27.579us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	44.276us	20	20	100.00
		pattgen_csr_aliasing	2.000s	45.337us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	29.463ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	2.571ms	50	50	100.00
V2	error	pattgen_error	3.000s	130.809us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.783m	56.840ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	10.845us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	31.203us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	914.484us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	914.484us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	17.079us	5	5	100.00
		pattgen_csr_rw	2.000s	44.276us	20	20	100.00
		pattgen_csr_aliasing	2.000s	45.337us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	31.535us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	17.079us	5	5	100.00
		pattgen_csr_rw	2.000s	44.276us	20	20	100.00
		pattgen_csr_aliasing	2.000s	45.337us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	31.535us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	949.820us	20	20	100.00
		pattgen_sec_cm	3.000s	61.286us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	949.820us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.400m	75.148ms	16	50	32.00
V3		TOTAL			16	50	32.00
	Unmapped tests	pattgen_inactive_level	1.867m	10.016ms	48	50	96.00
		TOTAL			534	570	93.68

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 28 failures:

Test pattgen_stress_all_with_rand_reset has 28 failures.

1.pattgen_stress_all_with_rand_reset.22466980841469074329094118930049715400457359494264982528404766822040168410005
Line 1404, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 281650562444 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 281650615602 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 281650615602 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 281650782270 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.34996901240732356567216330605711804807556330521359115132433159864524662257377
Line 702, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36002127640 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 36002137936 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 36002137936 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 36002221272 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 26 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 5.pattgen_stress_all_with_rand_reset.89175152483845730758153080088382353306386958509907408131706282058068628393728
    Line 306, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1447309394 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 6.pattgen_stress_all_with_rand_reset.98320228790886262220755733861034675135971148835569628356140476173084760108411
    Line 775, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74486770294 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 24.pattgen_inactive_level.44216435734081027402753794654772779890951282784053953904600741681427777247272
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10756710595 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x80095e90) == 0x0
  UVM_INFO @ 10756710595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.pattgen_inactive_level.108904701209435182647733511389241330381083351994381256304648158938800800495161
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10016186640 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcd022a50) == 0x0
  UVM_INFO @ 10016186640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```