PATTGEN Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 5.000s 94.171us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 2.000s 17.079us 5 5 100.00
V1 csr_rw pattgen_csr_rw 2.000s 44.276us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 4.000s 512.555us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 2.000s 45.337us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 3.000s 27.579us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 2.000s 44.276us 20 20 100.00
pattgen_csr_aliasing 2.000s 45.337us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 1.950m 29.463ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.867m 2.571ms 50 50 100.00
V2 error pattgen_error 3.000s 130.809us 50 50 100.00
V2 stress_all pattgen_stress_all 2.783m 56.840ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 10.845us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 31.203us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 914.484us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 914.484us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 2.000s 17.079us 5 5 100.00
pattgen_csr_rw 2.000s 44.276us 20 20 100.00
pattgen_csr_aliasing 2.000s 45.337us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 31.535us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 2.000s 17.079us 5 5 100.00
pattgen_csr_rw 2.000s 44.276us 20 20 100.00
pattgen_csr_aliasing 2.000s 45.337us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 31.535us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 949.820us 20 20 100.00
pattgen_sec_cm 3.000s 61.286us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 949.820us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 30.400m 75.148ms 16 50 32.00
V3 TOTAL 16 50 32.00
Unmapped tests pattgen_inactive_level 1.867m 10.016ms 48 50 96.00
TOTAL 534 570 93.68

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results