PATTGEN Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	6.000s	1.044ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	62.318us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	13.185us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	66.478us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	17.146us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	31.561us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	13.185us	20	20	100.00
		pattgen_csr_aliasing	3.000s	17.146us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.633m	14.615ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	5.265ms	50	50	100.00
V2	error	pattgen_error	4.000s	90.344us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.883m	16.644ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	22.089us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	74.163us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	164.130us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	164.130us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	62.318us	5	5	100.00
		pattgen_csr_rw	4.000s	13.185us	20	20	100.00
		pattgen_csr_aliasing	3.000s	17.146us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	66.417us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	62.318us	5	5	100.00
		pattgen_csr_rw	4.000s	13.185us	20	20	100.00
		pattgen_csr_aliasing	3.000s	17.146us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	66.417us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	76.826us	20	20	100.00
		pattgen_sec_cm	3.000s	127.292us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	76.826us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	45.583m	529.140ms	11	50	22.00
V3		TOTAL			11	50	22.00
	Unmapped tests	pattgen_inactive_level	1.467m	10.011ms	47	50	94.00
		TOTAL			528	570	92.63

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:

Test pattgen_stress_all_with_rand_reset has 38 failures.

0.pattgen_stress_all_with_rand_reset.47968186516820499864222806001175069007400192636392904261039578526505354089153
Line 498, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 301488015246 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 301488037506 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 301488037506 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 301488437506 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.109171302671089084340549130765076348762512358081377578983890669213949997631168
Line 575, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 271245194734 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 271245339647 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 271245339647 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 271247006317 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 36 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 9.pattgen_inactive_level.94670043193531025057373620604890793265172088290442819148304313222904626873384
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10011241702 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1f468c90) == 0x0
  UVM_INFO @ 10011241702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.pattgen_inactive_level.84041883527529445509108292606052990827051712970934482536475489956632041881774
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10005925804 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb8cdd950) == 0x0
  UVM_INFO @ 10005925804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 15.pattgen_stress_all_with_rand_reset.43840078405813501705009859227468418369236182868742413270247692036485809346893
    Line 546, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11667471735 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 33.pattgen_inactive_level.69410496016677828833553234158034043578641886498534884758435742058488252672009
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10004236181 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdedd6ad0) == 0x0
  UVM_INFO @ 10004236181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```