PATTGEN Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	710.666us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	30.826us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	11.000s	27.464us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	295.593us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	8.000s	30.622us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	95.596us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	11.000s	27.464us	20	20	100.00
		pattgen_csr_aliasing	8.000s	30.622us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.800m	4.247ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	2.635ms	50	50	100.00
V2	error	pattgen_error	3.000s	47.408us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.983m	2.736ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	15.097us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	11.831us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	18.000s	88.205us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	18.000s	88.205us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	30.826us	5	5	100.00
		pattgen_csr_rw	11.000s	27.464us	20	20	100.00
		pattgen_csr_aliasing	8.000s	30.622us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	61.152us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	30.826us	5	5	100.00
		pattgen_csr_rw	11.000s	27.464us	20	20	100.00
		pattgen_csr_aliasing	8.000s	30.622us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	61.152us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	174.713us	20	20	100.00
		pattgen_sec_cm	3.000s	207.990us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	174.713us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	34.317m	614.457ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	5.433m	10.005ms	45	50	90.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.7250975822996527335951925178222051114541354073601221598161743326645193040391
Line 1290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 64513404358 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 64513405881 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 64513405881 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 64513452941 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.24791570738394381545062519277228195561174308327980253126603862749191153626830
Line 357, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4697962548 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4697964226 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4697964226 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 4698170110 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 4 failures:
- Test pattgen_inactive_level has 4 failures.
  - 14.pattgen_inactive_level.8483432036027190720798158200023790209468384052571630901008839840198883244611
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10135374047 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2389e110) == 0x0
  UVM_INFO @ 10135374047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.pattgen_inactive_level.76488360121037493241431746012530480886964463816799841033002847977274620275386
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10004935686 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x81017210) == 0x0
  UVM_INFO @ 10004935686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 14.pattgen_stress_all_with_rand_reset.66040403215725695391315854623307650285159178263904600849775706951302246062487
    Line 874, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29479822145 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 26.pattgen_stress_all_with_rand_reset.20608067660743308711670234038582146819935486006437607557094139922763572477818
    Line 419, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12031490763 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 1.pattgen_inactive_level.20640278563427697577198990786046673792825008508329219874827845896567777485274
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10011287097 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf0333e50) == 0x0
  UVM_INFO @ 10011287097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```