PATTGEN Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 7.000s 214.448us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 2.000s 12.104us 5 5 100.00
V1 csr_rw pattgen_csr_rw 7.000s 11.918us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 7.000s 537.694us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 7.000s 16.696us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 12.000s 72.769us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 7.000s 11.918us 20 20 100.00
pattgen_csr_aliasing 7.000s 16.696us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 1.983m 3.179ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.933m 14.602ms 50 50 100.00
V2 error pattgen_error 4.000s 113.944us 50 50 100.00
V2 stress_all pattgen_stress_all 3.900m 5.604ms 50 50 100.00
V2 alert_test pattgen_alert_test 7.000s 52.992us 50 50 100.00
V2 intr_test pattgen_intr_test 12.000s 22.753us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 20.000s 512.152us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 20.000s 512.152us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 2.000s 12.104us 5 5 100.00
pattgen_csr_rw 7.000s 11.918us 20 20 100.00
pattgen_csr_aliasing 7.000s 16.696us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 12.605us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 2.000s 12.104us 5 5 100.00
pattgen_csr_rw 7.000s 11.918us 20 20 100.00
pattgen_csr_aliasing 7.000s 16.696us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 12.605us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 8.000s 272.621us 20 20 100.00
pattgen_sec_cm 3.000s 37.440us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 8.000s 272.621us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 39.250m 778.261ms 15 50 30.00
V3 TOTAL 15 50 30.00
Unmapped tests pattgen_inactive_level 26.000s 10.045ms 48 50 96.00
TOTAL 533 570 93.51

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results