PATTGEN Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	214.448us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	12.104us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	11.918us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	7.000s	537.694us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	7.000s	16.696us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	72.769us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	11.918us	20	20	100.00
		pattgen_csr_aliasing	7.000s	16.696us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.983m	3.179ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	14.602ms	50	50	100.00
V2	error	pattgen_error	4.000s	113.944us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.900m	5.604ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	52.992us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	22.753us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	20.000s	512.152us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	20.000s	512.152us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	12.104us	5	5	100.00
		pattgen_csr_rw	7.000s	11.918us	20	20	100.00
		pattgen_csr_aliasing	7.000s	16.696us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	12.605us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	12.104us	5	5	100.00
		pattgen_csr_rw	7.000s	11.918us	20	20	100.00
		pattgen_csr_aliasing	7.000s	16.696us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	12.605us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	272.621us	20	20	100.00
		pattgen_sec_cm	3.000s	37.440us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	272.621us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	39.250m	778.261ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	26.000s	10.045ms	48	50	96.00
		TOTAL			533	570	93.51

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.17848244615611951680254536028301400102066588181302703063149730887965919301196
Line 386, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 24030601949 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 24030657257 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 24030657257 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 24030990589 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.22424336038879897313986240108575202012879220682081795672274266881502611858758
Line 292, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 240426893 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 240430585 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 240430585 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 240504267 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 12.pattgen_stress_all_with_rand_reset.113992283464021464809970169955843117320579001551693171321199432509420559490993
    Line 315, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 332246747 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 19.pattgen_stress_all_with_rand_reset.32112709616671066137392892016658798928704470258805729007926550305227245451082
    Line 1381, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 322882482528 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 24.pattgen_inactive_level.110103339870215055886795829012728804221547955224566021023293465465975101518978
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10097671345 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa54e890) == 0x0
  UVM_INFO @ 10097671345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.pattgen_inactive_level.20098726804549749554496329698534262964331352105154669724343704638505781365562
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10044767953 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb6876d50) == 0x0
  UVM_INFO @ 10044767953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```