PATTGEN Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	474.149us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	109.194us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	50.720us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	347.844us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	38.846us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	68.449us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	50.720us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.846us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.100m	15.486ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	10.908ms	50	50	100.00
V2	error	pattgen_error	7.000s	38.301us	49	50	98.00
V2	stress_all	pattgen_stress_all	4.950m	24.641ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	50.752us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	16.123us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	341.499us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	341.499us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	109.194us	5	5	100.00
		pattgen_csr_rw	3.000s	50.720us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.846us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	60.783us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	109.194us	5	5	100.00
		pattgen_csr_rw	3.000s	50.720us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.846us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	60.783us	20	20	100.00
V2		TOTAL			339	340	99.71
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	80.017us	20	20	100.00
		pattgen_sec_cm	4.000s	38.548us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	80.017us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.667m	102.279ms	19	50	38.00
V3		TOTAL			19	50	38.00
	Unmapped tests	pattgen_inactive_level	5.333m	10.012ms	48	50	96.00
		TOTAL			536	570	94.04

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	7	87.50
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

Test pattgen_stress_all_with_rand_reset has 26 failures.

0.pattgen_stress_all_with_rand_reset.76230673014458673533283940437710161042050017788275880066328883157381580380254
Line 756, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16932507545 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 16932511032 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16932511032 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 16932616292 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.8901911868286610364324929975085903795193262429267990032286337271271819540560
Line 386, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 21748353111 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 21748399447 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 21748399447 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 21748685163 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 24 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 11.pattgen_stress_all_with_rand_reset.33096199858304830492654338740343570106882355419258002386111311787297487305542
    Line 383, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105838598271 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 23.pattgen_stress_all_with_rand_reset.68198803289903485340442939339155547516508685397206788815313270374061896701046
    Line 299, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 384912835 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 10.pattgen_inactive_level.42254818934967951841880069266777650818594078279140093993115083522659752230627
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10011920849 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc4a04210) == 0x0
  UVM_INFO @ 10011920849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.pattgen_inactive_level.44749884842789515220252490119979966801547293574746325925195045341855732241068
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015011576 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x73f6c550) == 0x0
  UVM_INFO @ 10015011576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:249) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_error has 1 failures.
  - 22.pattgen_error.51032182833695949815144390668974225129914897493050812726823701845976603597646
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_error/latest/run.log
```
  UVM_ERROR @ 148498292 ps: (pattgen_scoreboard.sv:249) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10073
```