PATTGEN Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	14.000s	235.959us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	14.351us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	18.899us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	279.848us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	58.524us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	24.663us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	18.899us	20	20	100.00
		pattgen_csr_aliasing	3.000s	58.524us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.833m	18.788ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	5.265ms	50	50	100.00
V2	error	pattgen_error	13.000s	38.937us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.083m	4.127ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	100.395us	50	50	100.00
V2	intr_test	pattgen_intr_test	11.000s	25.868us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	18.000s	165.308us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	18.000s	165.308us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	14.351us	5	5	100.00
		pattgen_csr_rw	7.000s	18.899us	20	20	100.00
		pattgen_csr_aliasing	3.000s	58.524us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	23.363us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	14.351us	5	5	100.00
		pattgen_csr_rw	7.000s	18.899us	20	20	100.00
		pattgen_csr_aliasing	3.000s	58.524us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	23.363us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	48.838us	20	20	100.00
		pattgen_sec_cm	3.000s	118.809us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	48.838us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	26.983m	266.858ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	5.750m	10.109ms	45	50	90.00
		TOTAL			527	570	92.46

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 35 failures:

Test pattgen_stress_all_with_rand_reset has 35 failures.

0.pattgen_stress_all_with_rand_reset.19397134597071101223332123997116598909537221633858485109935098123701242789710
Line 489, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16827307122 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 16827323222 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16827323222 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 16827406554 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.65593764732224961128983597737341321655940838465752141662174545617494303064791
Line 301, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2229808326 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2229808431 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2229808431 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 2229912596 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 33 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 4 failures:
- Test pattgen_inactive_level has 4 failures.
  - 13.pattgen_inactive_level.106243645377916386459918752367889065210134881525459818396656396789646151797924
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10108791939 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa9ca1290) == 0x0
  UVM_INFO @ 10108791939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.pattgen_inactive_level.72356050117359394145002860964503560021757932028143513582648450815216430798228
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10279496232 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2fa47210) == 0x0
  UVM_INFO @ 10279496232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 8.pattgen_stress_all_with_rand_reset.4665363287581814979607272545604294076663886649319540554163884376044321209440
    Line 633, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21808336204 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 15.pattgen_stress_all_with_rand_reset.77454309924403489014728128812998046411407295542538318717060967096810899372383
    Line 1038, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59955096241 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 45.pattgen_inactive_level.29172365206572878764563293508288143172400691576307791562297089124393958399731
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10011827386 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x35ad690) == 0x0
  UVM_INFO @ 10011827386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```