PATTGEN Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	543.608us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	43.390us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	27.003us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	478.087us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	64.321us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	24.105us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	27.003us	20	20	100.00
		pattgen_csr_aliasing	3.000s	64.321us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.833m	18.783ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.750m	5.371ms	50	50	100.00
V2	error	pattgen_error	4.000s	75.172us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.550m	5.320ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	24.840us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	17.892us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	37.584us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	37.584us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	43.390us	5	5	100.00
		pattgen_csr_rw	3.000s	27.003us	20	20	100.00
		pattgen_csr_aliasing	3.000s	64.321us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	76.699us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	43.390us	5	5	100.00
		pattgen_csr_rw	3.000s	27.003us	20	20	100.00
		pattgen_csr_aliasing	3.000s	64.321us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	76.699us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	52.915us	20	20	100.00
		pattgen_sec_cm	4.000s	37.306us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	52.915us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	46.467m	477.262ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	5.600m	10.034ms	48	50	96.00
		TOTAL			530	570	92.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

0.pattgen_stress_all_with_rand_reset.11309584670826608670930588669048387959780112203832443507002059367891232924304
Line 303, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1213359781 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1213369221 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1213369221 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 1213744224 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.11010012796893909821660834411073928430682420425399272227759592073448518984737
Line 304, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2490543066 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2490548472 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2490548472 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 2491457562 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 17.pattgen_stress_all_with_rand_reset.40985774564168606333935232651668372090483410848942582593181023976688179839824
    Line 649, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41566444585 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 18.pattgen_stress_all_with_rand_reset.29686299523189052591491999475424079389706779737137066203717695253584486702535
    Line 458, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7213833416 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 9.pattgen_inactive_level.52965790246905086440345806973555688324300655231365924307907000787843734941742
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10025094126 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3d2e7610) == 0x0
  UVM_INFO @ 10025094126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 14.pattgen_inactive_level.103030523917991404886663264558879115030083877883499300217243542737325652760603
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10033817648 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xeecc7790) == 0x0
  UVM_INFO @ 10033817648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```