PATTGEN Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	1.736ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	62.018us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	14.683us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.105ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	50.916us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	107.181us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	14.683us	20	20	100.00
		pattgen_csr_aliasing	3.000s	50.916us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.933m	3.950ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	5.267ms	50	50	100.00
V2	error	pattgen_error	12.000s	44.751us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.567m	106.529ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	19.857us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	27.603us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	128.007us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	128.007us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	62.018us	5	5	100.00
		pattgen_csr_rw	2.000s	14.683us	20	20	100.00
		pattgen_csr_aliasing	3.000s	50.916us	5	5	100.00
		pattgen_same_csr_outstanding	6.000s	18.844us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	62.018us	5	5	100.00
		pattgen_csr_rw	2.000s	14.683us	20	20	100.00
		pattgen_csr_aliasing	3.000s	50.916us	5	5	100.00
		pattgen_same_csr_outstanding	6.000s	18.844us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	67.935us	20	20	100.00
		pattgen_sec_cm	2.000s	58.520us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	67.935us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	34.783m	82.400ms	18	50	36.00
V3		TOTAL			18	50	36.00
	Unmapped tests	pattgen_inactive_level	1.333m	10.005ms	46	50	92.00
		TOTAL			534	570	93.68

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

Test pattgen_stress_all_with_rand_reset has 26 failures.

1.pattgen_stress_all_with_rand_reset.26858337560937980968158567078093917832942394607770864562619991472450648825413
Line 567, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38837766082 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 38837793239 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 38837793239 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 38837993239 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.108970231745512168282561415260562462910090809483996200101371601174838500476390
Line 971, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32113304778 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 32113309149 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 32113309149 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 32113340400 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 24 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 9.pattgen_stress_all_with_rand_reset.93740316350672821478853606608200561584520069174515640781303701969002387901560
    Line 306, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 144184483 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 21.pattgen_stress_all_with_rand_reset.72664794170807457173603758230429739993944429545542323220022390077439519284074
    Line 312, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1658445584 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 21.pattgen_inactive_level.71789405340750427566326539325683794557169965328304592544095134080306796225776
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10005085246 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x337a0910) == 0x0
  UVM_INFO @ 10005085246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.pattgen_inactive_level.27409410845984180326746713480404903345051605934253393479170717599667680389010
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10053407886 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xae4c1ed0) == 0x0
  UVM_INFO @ 10053407886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 30.pattgen_inactive_level.10930694466767134018180227659835739383996430228503039064892091622613658899236
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10041447409 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x43703bd0) == 0x0
  UVM_INFO @ 10041447409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.pattgen_inactive_level.101775496273454976425030971591314809271828960851396049619982516716050530565779
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10074560323 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xaec132d0) == 0x0
  UVM_INFO @ 10074560323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```