PATTGEN Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	353.944us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	17.457us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	48.150us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	262.368us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	34.221us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	32.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	48.150us	20	20	100.00
		pattgen_csr_aliasing	3.000s	34.221us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.633m	16.446ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	26.307ms	50	50	100.00
V2	error	pattgen_error	4.000s	73.436us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.833m	8.317ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	24.249us	50	50	100.00
V2	intr_test	pattgen_intr_test	5.000s	48.260us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	45.003us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	45.003us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	17.457us	5	5	100.00
		pattgen_csr_rw	4.000s	48.150us	20	20	100.00
		pattgen_csr_aliasing	3.000s	34.221us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	126.462us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	17.457us	5	5	100.00
		pattgen_csr_rw	4.000s	48.150us	20	20	100.00
		pattgen_csr_aliasing	3.000s	34.221us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	126.462us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	80.271us	20	20	100.00
		pattgen_sec_cm	3.000s	65.422us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	80.271us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	31.567m	128.879ms	17	50	34.00
V3		TOTAL			17	50	34.00
	Unmapped tests	pattgen_inactive_level	1.550m	10.009ms	48	50	96.00
		TOTAL			535	570	93.86

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

1.pattgen_stress_all_with_rand_reset.107460375887738848435861395811682847588671461406499346917728457667450598506614
Line 424, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6301787559 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 6301791174 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6301791174 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 6301871982 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.61534766003461874669824451331875084251800065338771548491724887953486763613850
Line 759, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 183783627153 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 183783636528 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 183783636528 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 183783969864 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 20.pattgen_stress_all_with_rand_reset.69265180356573154973094637406229115988620101554722687609896884295407641133919
    Line 502, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12674767558 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 32.pattgen_stress_all_with_rand_reset.108398824742899416899158943636321732496353617265482926018828881192973579966939
    Line 303, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 577300981 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 18.pattgen_inactive_level.57709789976503239566500877748327974344213907128733725791003533677831944373176
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009029672 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb6c63b90) == 0x0
  UVM_INFO @ 10009029672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 26.pattgen_inactive_level.112057134952998154130314140839783644159973294061863051453889325837400891762370
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008908022 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5baf2e10) == 0x0
  UVM_INFO @ 10008908022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```