PATTGEN Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	60.139us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	69.155us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	15.245us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	127.914us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	104.995us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	16.971us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	15.245us	20	20	100.00
		pattgen_csr_aliasing	3.000s	104.995us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.900m	10.539ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	2.687ms	50	50	100.00
V2	error	pattgen_error	12.000s	121.518us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.783m	11.524ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	42.017us	50	50	100.00
V2	intr_test	pattgen_intr_test	13.000s	178.209us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	51.724us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	51.724us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	69.155us	5	5	100.00
		pattgen_csr_rw	12.000s	15.245us	20	20	100.00
		pattgen_csr_aliasing	3.000s	104.995us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	74.407us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	69.155us	5	5	100.00
		pattgen_csr_rw	12.000s	15.245us	20	20	100.00
		pattgen_csr_aliasing	3.000s	104.995us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	74.407us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	93.097us	20	20	100.00
		pattgen_sec_cm	3.000s	64.647us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	93.097us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.117m	102.599ms	10	50	20.00
V3		TOTAL			10	50	20.00
	Unmapped tests	pattgen_inactive_level	5.533m	10.015ms	48	50	96.00
		TOTAL			528	570	92.63

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 37 failures:

Test pattgen_stress_all_with_rand_reset has 37 failures.

0.pattgen_stress_all_with_rand_reset.84816895504866873035064485330426601547197798444811874334990363066181807533648
Line 687, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 21761916929 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 21761921841 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 21761921841 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 21761984343 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.16686176578544026644660195052526534760332223697490202488192658048972842879633
Line 374, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10760843895 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 10760866139 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 10760866139 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 10761266139 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 35 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 1.pattgen_stress_all_with_rand_reset.73403951187598968258342332796214445081537232946041026607842209682546886654931
    Line 456, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22369299892 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 2.pattgen_stress_all_with_rand_reset.5083106851039251318760494059601821413665408530393370082540773991058050983675
    Line 395, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8848166070 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 35.pattgen_inactive_level.80686678166684719738444443501308793628568399147087948012617226704235658335156
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10071508223 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3b4b34d0) == 0x0
  UVM_INFO @ 10071508223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.pattgen_inactive_level.104331801471470437180241489778503773955356901446877876061478024824551649333462
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015174072 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xaf0c11d0) == 0x0
  UVM_INFO @ 10015174072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```