PATTGEN Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	507.601us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	49.775us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	24.441us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	245.329us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	15.435us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	58.664us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	24.441us	20	20	100.00
		pattgen_csr_aliasing	3.000s	15.435us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.917m	10.538ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.967m	10.526ms	50	50	100.00
V2	error	pattgen_error	4.000s	152.405us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.867m	4.069ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	155.240us	50	50	100.00
V2	intr_test	pattgen_intr_test	2.000s	29.973us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	138.081us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	138.081us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	49.775us	5	5	100.00
		pattgen_csr_rw	2.000s	24.441us	20	20	100.00
		pattgen_csr_aliasing	3.000s	15.435us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	368.775us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	49.775us	5	5	100.00
		pattgen_csr_rw	2.000s	24.441us	20	20	100.00
		pattgen_csr_aliasing	3.000s	15.435us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	368.775us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	161.676us	20	20	100.00
		pattgen_sec_cm	3.000s	259.230us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	161.676us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	31.183m	130.828ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	1.017m	10.064ms	48	50	96.00
		TOTAL			530	570	92.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

1.pattgen_stress_all_with_rand_reset.108488510227143828204569306355767816239397925090289037594349183801589775761742
Line 313, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3736275415 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3736300729 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3736300729 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 3736856284 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

6.pattgen_stress_all_with_rand_reset.78876378062285189638321862336465571137350730800798097120070305929236635171019
Line 501, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 27138560472 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 27138571669 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 27138571669 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 27138717500 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 8.pattgen_stress_all_with_rand_reset.56960404918131713423427510999930125562622199288508981553784932102050592350493
    Line 675, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25037980004 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 15.pattgen_stress_all_with_rand_reset.83687864034836500113293863532389375034056593541888651645967593736894047115040
    Line 869, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 389321673843 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 15.pattgen_inactive_level.106206773353223877203145138639118544420902916699194327832393681826680668461330
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10181995499 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf02dc690) == 0x0
  UVM_INFO @ 10181995499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.pattgen_inactive_level.56353811935581153626149438515736264136691940463793023632174822111560145690383
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10063730896 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x621042d0) == 0x0
  UVM_INFO @ 10063730896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```