PATTGEN Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	6.000s	794.324us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	30.944us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	54.585us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	297.030us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	30.622us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	118.638us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	54.585us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.622us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.917m	2.694ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	7.741ms	50	50	100.00
V2	error	pattgen_error	4.000s	32.853us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.900m	8.639ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	23.199us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	54.857us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	247.975us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	247.975us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	30.944us	5	5	100.00
		pattgen_csr_rw	2.000s	54.585us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.622us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	86.141us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	30.944us	5	5	100.00
		pattgen_csr_rw	2.000s	54.585us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.622us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	86.141us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	512.390us	20	20	100.00
		pattgen_sec_cm	2.000s	58.380us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	512.390us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.250m	71.958ms	17	50	34.00
V3		TOTAL			17	50	34.00
	Unmapped tests	pattgen_inactive_level	31.000s	10.070ms	48	50	96.00
		TOTAL			535	570	93.86

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

0.pattgen_stress_all_with_rand_reset.84582876462286599930291590760795009156129597848674377603639067440318100355950
Line 500, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 41116548238 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 41116569450 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 41116569450 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 41116761760 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.62046233905051308602709509088179386370179030407917111091589127912633279323516
Line 290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 414697129 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 414720278 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 414720278 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 414920278 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 20.pattgen_stress_all_with_rand_reset.43933233588249356273710749065124153846834265902526722970684597342335980626840
    Line 306, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107577896 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 38.pattgen_stress_all_with_rand_reset.39057003072642431235913755902018575622447584803151278301491655872315506924074
    Line 431, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10274490107 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 21.pattgen_inactive_level.26117308531268814048662342432362496388587573504838435838167567074863048217495
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10070004727 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x23eebb10) == 0x0
  UVM_INFO @ 10070004727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.pattgen_inactive_level.62752698399821698982444393787112140997309880151485897682390137114822569546374
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10074553070 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa22dd090) == 0x0
  UVM_INFO @ 10074553070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```