PATTGEN Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	31.891us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	31.504us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	15.521us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	777.091us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	27.271us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	50.662us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	15.521us	20	20	100.00
		pattgen_csr_aliasing	3.000s	27.271us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.650m	15.776ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	32.862ms	50	50	100.00
V2	error	pattgen_error	10.000s	101.041us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.717m	21.228ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	21.760us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	22.415us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	43.527us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	43.527us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	31.504us	5	5	100.00
		pattgen_csr_rw	12.000s	15.521us	20	20	100.00
		pattgen_csr_aliasing	3.000s	27.271us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	48.146us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	31.504us	5	5	100.00
		pattgen_csr_rw	12.000s	15.521us	20	20	100.00
		pattgen_csr_aliasing	3.000s	27.271us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	48.146us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	37.915us	20	20	100.00
		pattgen_sec_cm	3.000s	37.226us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	37.915us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	45.183m	105.255ms	19	50	38.00
V3		TOTAL			19	50	38.00
	Unmapped tests	pattgen_inactive_level	5.283m	10.002ms	45	50	90.00
		TOTAL			534	570	93.68

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

Test pattgen_stress_all_with_rand_reset has 26 failures.

0.pattgen_stress_all_with_rand_reset.73397054924188059853415243980012736900015365593563365709700429607978257380230
Line 812, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 51458859584 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 51458873359 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 51458873359 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 6/10
  UVM_INFO @ 51459036623 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.86772451232187671613040669467072455129401942430866352956828967547155097689734
Line 644, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26888563517 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 26888567457 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 26888567457 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 6/10
  UVM_INFO @ 26888689905 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 24 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 4 failures:
- Test pattgen_inactive_level has 4 failures.
  - 13.pattgen_inactive_level.113815077863191373920849289593741949111790825627237041160038850295671671020452
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10020244638 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcd134590) == 0x0
  UVM_INFO @ 10020244638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.pattgen_inactive_level.60212988129478619532453013215846238976455536120034890438777942470450256525961
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10057076287 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfed18210) == 0x0
  UVM_INFO @ 10057076287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 22.pattgen_stress_all_with_rand_reset.54985256333355623761183513201299583012543543142458285471144922721181913470663
    Line 533, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14719840461 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 26.pattgen_stress_all_with_rand_reset.96197304292713022447458562421462721187042010624237206816407229930448340520465
    Line 306, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 577486447 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 15.pattgen_inactive_level.5560113445777284014907012996230599516254944968546773789370726786660549060831
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10023276302 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x34546ed0) == 0x0
  UVM_INFO @ 10023276302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:249) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 40.pattgen_stress_all_with_rand_reset.111209352424395987276407463559556445809552116156448599336136456622209008529352
    Line 774, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107524679860 ps: (pattgen_scoreboard.sv:249) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @11831
```