aad711e1bc
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pattgen_smoke | 13.000s | 201.809us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pattgen_csr_hw_reset | 7.000s | 25.528us | 5 | 5 | 100.00 |
V1 | csr_rw | pattgen_csr_rw | 12.000s | 54.446us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 921.310us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 15.602us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 7.000s | 26.440us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 12.000s | 54.446us | 20 | 20 | 100.00 |
pattgen_csr_aliasing | 3.000s | 15.602us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | perf | pattgen_perf | 2.783m | 16.443ms | 50 | 50 | 100.00 |
V2 | cnt_rollover | cnt_rollover | 1.867m | 5.264ms | 50 | 50 | 100.00 |
V2 | error | pattgen_error | 7.000s | 19.184us | 50 | 50 | 100.00 |
V2 | stress_all | pattgen_stress_all | 4.567m | 27.879ms | 50 | 50 | 100.00 |
V2 | alert_test | pattgen_alert_test | 3.000s | 33.359us | 50 | 50 | 100.00 |
V2 | intr_test | pattgen_intr_test | 7.000s | 14.209us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pattgen_tl_errors | 9.000s | 85.818us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pattgen_tl_errors | 9.000s | 85.818us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 7.000s | 25.528us | 5 | 5 | 100.00 |
pattgen_csr_rw | 12.000s | 54.446us | 20 | 20 | 100.00 | ||
pattgen_csr_aliasing | 3.000s | 15.602us | 5 | 5 | 100.00 | ||
pattgen_same_csr_outstanding | 7.000s | 53.134us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pattgen_csr_hw_reset | 7.000s | 25.528us | 5 | 5 | 100.00 |
pattgen_csr_rw | 12.000s | 54.446us | 20 | 20 | 100.00 | ||
pattgen_csr_aliasing | 3.000s | 15.602us | 5 | 5 | 100.00 | ||
pattgen_same_csr_outstanding | 7.000s | 53.134us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 340 | 340 | 100.00 | |||
V2S | tl_intg_err | pattgen_tl_intg_err | 7.000s | 41.109us | 20 | 20 | 100.00 |
pattgen_sec_cm | 2.000s | 281.842us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 7.000s | 41.109us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 34.533m | 746.289ms | 12 | 50 | 24.00 |
V3 | TOTAL | 12 | 50 | 24.00 | |||
Unmapped tests | pattgen_inactive_level | 5.683m | 10.002ms | 48 | 50 | 96.00 | |
TOTAL | 530 | 570 | 92.98 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
N.A. | 1 | 1 | 0 | 0.00 |
V1 | 6 | 6 | 6 | 100.00 |
V2 | 8 | 8 | 8 | 100.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.88 | 100.00 | 100.00 | 100.00 | 99.16 | 96.13 | -- | 100.00 | 89.95 |
UVM_ERROR (cip_base_vseq.sv:826) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 32 failures:
1.pattgen_stress_all_with_rand_reset.103410634624445740592039799944645709198113433338518220802599599929375242604362
Line 996, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 118688740082 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 118688767689 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 118688767689 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Reset is issued for run 7/10
UVM_INFO @ 118688892690 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
2.pattgen_stress_all_with_rand_reset.23759611669294301178266632815678509629297984117940674733317225681286069686074
Line 295, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3373888485 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3373927760 ps: (cip_base_vseq.sv:750) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3373927760 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Reset is issued for run 1/5
UVM_INFO @ 3374094428 ps: (cip_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 30 more failures.
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard]
has 6 failures:
16.pattgen_stress_all_with_rand_reset.50116069151919149400723268146479400729010876790294087926774829600540786437681
Line 321, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6148615363 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
24.pattgen_stress_all_with_rand_reset.99631578687376682367336576328924220803307377646550999309484054713691512355052
Line 889, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32395606642 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == *
has 1 failures:
41.pattgen_inactive_level.32416383493927007373612142877204529112502515803300000960088646119866647101236
Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10038912162 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe60d1790) == 0x0
UVM_INFO @ 10038912162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == *
has 1 failures:
45.pattgen_inactive_level.10057294420843733723614992351856092368864158305174954430157995238401013236173
Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10001602776 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x1f1c6910) == 0x0
UVM_INFO @ 10001602776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---