PATTGEN Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	704.991us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	18.134us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	53.400us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	106.493us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	18.352us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	65.642us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	53.400us	20	20	100.00
		pattgen_csr_aliasing	2.000s	18.352us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.933m	17.151ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	10.522ms	50	50	100.00
V2	error	pattgen_error	3.000s	34.620us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.550m	88.185ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	44.079us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	36.084us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	252.872us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	252.872us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	18.134us	5	5	100.00
		pattgen_csr_rw	3.000s	53.400us	20	20	100.00
		pattgen_csr_aliasing	2.000s	18.352us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	48.429us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	18.134us	5	5	100.00
		pattgen_csr_rw	3.000s	53.400us	20	20	100.00
		pattgen_csr_aliasing	2.000s	18.352us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	48.429us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	80.214us	20	20	100.00
		pattgen_sec_cm	2.000s	36.430us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	80.214us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	34.450m	103.733ms	16	50	32.00
V3		TOTAL			16	50	32.00
	Unmapped tests	pattgen_inactive_level	5.267m	10.009ms	46	50	92.00
		TOTAL			532	570	93.33

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.63461734335411428823378247613855457796254583524134449130505104036468988002187
Line 1357, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 56696804481 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 56696812795 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 56696812795 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 56696892795 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

5.pattgen_stress_all_with_rand_reset.35140397565299302203009375293494901539076415621438552365192230962210245251519
Line 398, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 35534647539 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 35534705402 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 35534705402 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 35534848260 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 4.pattgen_stress_all_with_rand_reset.42444557859361600534449676940947320887142012385030516623970988339242614410594
    Line 633, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 181386177184 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 8.pattgen_stress_all_with_rand_reset.40980496882462995377339367246905115841028673131673580745624546067871310151551
    Line 304, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 358806603 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 3 failures:
- Test pattgen_inactive_level has 3 failures.
  - 13.pattgen_inactive_level.101684030037857914937914697695985688169369011160908568204818683033126468275365
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10024648872 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd2fefa50) == 0x0
  UVM_INFO @ 10024648872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.pattgen_inactive_level.2656484284098232044804328854633900327675700201782050422393271818908514430899
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10014889834 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xe1592bd0) == 0x0
  UVM_INFO @ 10014889834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*) == * has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 15.pattgen_inactive_level.86883899958278188164563383409432708533164333118142279143335950961781247155278
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008936841 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd81f30d0) == 0x0
  UVM_INFO @ 10008936841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```