PATTGEN Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	550.572us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	191.483us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	14.430us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	249.346us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	26.246us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	6.000s	53.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	14.430us	20	20	100.00
		pattgen_csr_aliasing	3.000s	26.246us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	5.485ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	2.715ms	50	50	100.00
V2	error	pattgen_error	9.000s	17.602us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.883m	3.977ms	50	50	100.00
V2	alert_test	pattgen_alert_test	5.000s	55.587us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	11.248us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	550.872us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	550.872us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	191.483us	5	5	100.00
		pattgen_csr_rw	3.000s	14.430us	20	20	100.00
		pattgen_csr_aliasing	3.000s	26.246us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	52.755us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	191.483us	5	5	100.00
		pattgen_csr_rw	3.000s	14.430us	20	20	100.00
		pattgen_csr_aliasing	3.000s	26.246us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	52.755us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	315.296us	20	20	100.00
		pattgen_sec_cm	3.000s	228.331us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	315.296us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.000m	350.695ms	10	50	20.00
V3		TOTAL			10	50	20.00
	Unmapped tests	pattgen_inactive_level	1.567m	10.002ms	46	50	92.00
		TOTAL			526	570	92.28

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:

Test pattgen_stress_all_with_rand_reset has 39 failures.

0.pattgen_stress_all_with_rand_reset.22817532592738488020232466276464406471158202356821568996124671392238649296884
Line 875, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 51886351040 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 51886353569 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 51886353569 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 51886374187 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.11423487146946872252347512064988421282300904046402734436322923934901602206138
Line 1276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 664270390733 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 664270422775 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 664270422775 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 7/10
  UVM_INFO @ 664270756107 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 37 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 3.pattgen_inactive_level.7697449854378880915581229098683077291761985277818605239088089246052798861037
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10042417592 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x60d6eb10, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10042417592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.pattgen_inactive_level.104128855708974972790555110928747388287434416108655648766519498670465243724460
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10034699815 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf254d550, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10034699815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 2.pattgen_inactive_level.92299461928274407034329702455870010893200292020452413251023635924191442166864
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10028166085 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd8f79a50, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10028166085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 14.pattgen_inactive_level.104780508718987202803536927750214812299292349620871818971323401315686362214611
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10001962892 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x7c9e7850, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10001962892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 31.pattgen_stress_all_with_rand_reset.19131059556471986267059731653078593373617909140846225004479831558456235138756
    Line 319, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1461718637 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```