PATTGEN Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 7.000s 550.572us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 191.483us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 14.430us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 249.346us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 26.246us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 6.000s 53.849us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 14.430us 20 20 100.00
pattgen_csr_aliasing 3.000s 26.246us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 1.950m 5.485ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.833m 2.715ms 50 50 100.00
V2 error pattgen_error 9.000s 17.602us 50 50 100.00
V2 stress_all pattgen_stress_all 2.883m 3.977ms 50 50 100.00
V2 alert_test pattgen_alert_test 5.000s 55.587us 50 50 100.00
V2 intr_test pattgen_intr_test 7.000s 11.248us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 6.000s 550.872us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 6.000s 550.872us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 191.483us 5 5 100.00
pattgen_csr_rw 3.000s 14.430us 20 20 100.00
pattgen_csr_aliasing 3.000s 26.246us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 52.755us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 191.483us 5 5 100.00
pattgen_csr_rw 3.000s 14.430us 20 20 100.00
pattgen_csr_aliasing 3.000s 26.246us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 52.755us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 315.296us 20 20 100.00
pattgen_sec_cm 3.000s 228.331us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 315.296us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 37.000m 350.695ms 10 50 20.00
V3 TOTAL 10 50 20.00
Unmapped tests pattgen_inactive_level 1.567m 10.002ms 46 50 92.00
TOTAL 526 570 92.28

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results