PATTGEN Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 9.000s 616.093us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 7.000s 13.446us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 24.590us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 201.981us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 2.000s 14.931us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 8.000s 46.077us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 24.590us 20 20 100.00
pattgen_csr_aliasing 2.000s 14.931us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.950m 7.897ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.883m 5.262ms 50 50 100.00
V2 error pattgen_error 3.000s 51.167us 50 50 100.00
V2 stress_all pattgen_stress_all 4.800m 13.240ms 50 50 100.00
V2 alert_test pattgen_alert_test 3.000s 13.367us 50 50 100.00
V2 intr_test pattgen_intr_test 7.000s 15.750us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 90.924us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 90.924us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 7.000s 13.446us 5 5 100.00
pattgen_csr_rw 3.000s 24.590us 20 20 100.00
pattgen_csr_aliasing 2.000s 14.931us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 64.763us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 7.000s 13.446us 5 5 100.00
pattgen_csr_rw 3.000s 24.590us 20 20 100.00
pattgen_csr_aliasing 2.000s 14.931us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 64.763us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 8.000s 176.460us 20 20 100.00
pattgen_sec_cm 4.000s 3.586ms 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 8.000s 176.460us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 40.183m 106.685ms 12 50 24.00
V3 TOTAL 12 50 24.00
Unmapped tests pattgen_inactive_level 1.900m 10.002ms 46 50 92.00
TOTAL 528 570 92.63

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results