PATTGEN Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	616.093us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	13.446us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	24.590us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	201.981us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	14.931us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	46.077us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	24.590us	20	20	100.00
		pattgen_csr_aliasing	2.000s	14.931us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.950m	7.897ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	5.262ms	50	50	100.00
V2	error	pattgen_error	3.000s	51.167us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.800m	13.240ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	13.367us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	15.750us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	90.924us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	90.924us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	13.446us	5	5	100.00
		pattgen_csr_rw	3.000s	24.590us	20	20	100.00
		pattgen_csr_aliasing	2.000s	14.931us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	64.763us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	13.446us	5	5	100.00
		pattgen_csr_rw	3.000s	24.590us	20	20	100.00
		pattgen_csr_aliasing	2.000s	14.931us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	64.763us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	176.460us	20	20	100.00
		pattgen_sec_cm	4.000s	3.586ms	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	176.460us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.183m	106.685ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	1.900m	10.002ms	46	50	92.00
		TOTAL			528	570	92.63

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

0.pattgen_stress_all_with_rand_reset.33836914374659958841029675937243773294030931013063934233771939934250688428715
Line 508, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16809941686 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 16809943644 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16809943644 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 16810040418 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.10191875870807335625008137970589547986811968514549155025110982765192551917198
Line 544, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 74916832158 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 74916870355 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 74916870355 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 74917087745 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 7 failures:
- Test pattgen_stress_all_with_rand_reset has 7 failures.
  - 4.pattgen_stress_all_with_rand_reset.14946334752585649461886907027062303742626721253411484875304482748099223802031
    Line 308, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 395123907 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 6.pattgen_stress_all_with_rand_reset.58456637875841851098926665395307004876498512490794047813716031262025112659388
    Line 723, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 71806197114 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 7.pattgen_inactive_level.40333467524768500176471192184814179722187547552685052217276997317175620495906
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10002298388 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x60a07850, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10002298388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 12.pattgen_inactive_level.15603209203431520977443988741586252167706310475954916123521489934695502590785
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010777783 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x607d3790, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10010777783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 36.pattgen_inactive_level.13933285267140855656623084737298569257051401975473757629487608912251676891972
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10223323316 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x84144a50, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10223323316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 40.pattgen_inactive_level.27514588451706308805375215797927803490758473133833550674750569523780814986700
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10064201251 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x290b0150, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10064201251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```