PATTGEN Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	138.184us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	18.006us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	14.323us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	358.345us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	14.852us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	57.958us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	14.323us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.852us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.617m	4.033ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	2.633ms	50	50	100.00
V2	error	pattgen_error	13.000s	47.492us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.433m	44.112ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	50.094us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	19.511us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	842.054us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	842.054us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	18.006us	5	5	100.00
		pattgen_csr_rw	4.000s	14.323us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.852us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	15.622us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	18.006us	5	5	100.00
		pattgen_csr_rw	4.000s	14.323us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.852us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	15.622us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	110.988us	20	20	100.00
		pattgen_sec_cm	3.000s	114.134us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	110.988us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	38.983m	431.853ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	1.183m	10.023ms	46	50	92.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

3.pattgen_stress_all_with_rand_reset.23900984475523158910029206517059696159384307221405705076610313775759292289056
Line 528, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18356789398 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 18356798244 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 18356798244 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 18356819078 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.83181267095362510322162808098066285916487293093179665911590593917171924333721
Line 386, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4094583964 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4094587026 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4094587026 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 4094691196 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 25.pattgen_stress_all_with_rand_reset.81821276235579961136681556280399967785366968293515067894175502483452397552938
    Line 313, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6100155762 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 39.pattgen_stress_all_with_rand_reset.70901701359427955918964218278898069690621640586075383691702419331984904133817
    Line 330, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14558568457 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 1.pattgen_inactive_level.15820596048778044667601069323377404312510318028705024976534459380045807966800
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10025723821 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc1aae410, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10025723821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 11.pattgen_inactive_level.103937204423585112179809856497566976381226886944848837909272223885538004573743
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10142768210 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x49afd150, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10142768210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 21.pattgen_inactive_level.46180422967307834481943825516546445846011168290322483347509694261362569792180
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10023287826 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5300fb90, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10023287826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 35.pattgen_inactive_level.37264677793747466987303924971337955739364354182528286758960285543772600694961
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10035934778 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9d55e9d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10035934778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```