PATTGEN Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	108.493us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	12.000s	160.647us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	21.474us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.154ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	18.255us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	145.813us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	21.474us	20	20	100.00
		pattgen_csr_aliasing	2.000s	18.255us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.683m	8.223ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	4.498ms	50	50	100.00
V2	error	pattgen_error	8.000s	131.185us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.783m	20.902ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	26.979us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	24.935us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	57.897us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	57.897us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	12.000s	160.647us	5	5	100.00
		pattgen_csr_rw	7.000s	21.474us	20	20	100.00
		pattgen_csr_aliasing	2.000s	18.255us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	33.455us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	12.000s	160.647us	5	5	100.00
		pattgen_csr_rw	7.000s	21.474us	20	20	100.00
		pattgen_csr_aliasing	2.000s	18.255us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	33.455us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	12.000s	181.877us	20	20	100.00
		pattgen_sec_cm	2.000s	245.951us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	12.000s	181.877us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.750m	297.201ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	5.983m	10.024ms	45	50	90.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.104803488845625097964375693331504335292633691091395650643939028374983601481600
Line 413, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3062107714 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3062114084 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3062114084 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 3062214084 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.1587537414220060606415347492189635040398524123266698673477909607288226644762
Line 976, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40696901891 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 40696903416 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 40696903416 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 8/10
  UVM_INFO @ 40697003416 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 19.pattgen_stress_all_with_rand_reset.61750225324024268766503421926990395634611777446563427023325207868758451355705
    Line 373, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3511312376 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 29.pattgen_stress_all_with_rand_reset.102201841471354022040910753835404201393588068650045711011899899997832845968936
    Line 650, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57319145085 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 24.pattgen_inactive_level.106809516563587728934386432175519730467904738523650055144599931428460243224524
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010902204 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x876fd90, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
  UVM_INFO @ 10010902204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 25.pattgen_inactive_level.31341211334863469202425692836307846268936651856050709020368880997454769828290
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009545929 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x16c92ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10009545929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 26.pattgen_inactive_level.73734254313916203442474947121502388888836761839106798635132429233078389510400
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10072779678 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5563cb50, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
  UVM_INFO @ 10072779678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 34.pattgen_inactive_level.51366970634966169094336123798243121299811757687150551328793744174647701670947
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10039348744 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x8946afd0, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10039348744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 39.pattgen_inactive_level.44697593091563355590957225275049112890131556434868388181207526830794458251525
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10024059297 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x494f53d0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
  UVM_INFO @ 10024059297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```