PATTGEN Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	174.506us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	12.338us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	18.007us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	252.502us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	19.253us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	120.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	18.007us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.253us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	10.524ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	2.715ms	50	50	100.00
V2	error	pattgen_error	19.000s	42.299us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.700m	26.561ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	41.930us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	188.626us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	13.000s	352.212us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	13.000s	352.212us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	12.338us	5	5	100.00
		pattgen_csr_rw	3.000s	18.007us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.253us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	35.584us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	12.338us	5	5	100.00
		pattgen_csr_rw	3.000s	18.007us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.253us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	35.584us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	324.378us	20	20	100.00
		pattgen_sec_cm	3.000s	435.169us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	324.378us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	41.733m	490.906ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	4.100m	10.015ms	40	50	80.00
		TOTAL			524	570	91.93

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.76187050513356487087298595523051448289093893820254163472902513783740674323948
Line 2149, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 487603858410 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 487603883001 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 487603883001 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 9/10
  UVM_INFO @ 487604073477 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.19107857442280176167960148977011041231076854244059516781006111210959955422338
Line 309, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1186900902 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1186901750 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1186901750 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1186964252 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 3.pattgen_stress_all_with_rand_reset.82183052374874517146225175393625008091238726626208990897846482305086196397095
    Line 424, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35755894245 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 7.pattgen_stress_all_with_rand_reset.92756471785505522546805455601978552294389268331896423185953868264559614839431
    Line 299, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1084740702 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.40301433030624026122670218099383337307026151776934634886271229158392685871279
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10185257895 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe4400450, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10185257895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 6.pattgen_inactive_level.103519012161229633478538004446912094601232436353291998108673300741092287817473
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10054273213 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xce0a3e10, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10054273213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 16.pattgen_inactive_level.103829485533667813705629527505137690601981854651471971980646353871991177109663
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10036605094 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x28738b90, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10036605094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 18.pattgen_inactive_level.30311822638813873564155501255496242701382953498307651814759784569883083773941
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10056532697 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x6acdbc90, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
  UVM_INFO @ 10056532697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 20.pattgen_inactive_level.40250609997550934665671057986305070895106567171234482725392385528329538066918
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10030942279 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb1ab1150, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10030942279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 22.pattgen_inactive_level.884191833271294413926536431191110429884803146371532007947391883619621588489
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10022825156 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1fdc24d0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10022825156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 26.pattgen_inactive_level.49003714355126860885841929094843206816947736302270492796473108208777234251607
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10014543490 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x80c12150, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10014543490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 37.pattgen_inactive_level.100602077737979563546488154147723081003729706780452815767858550788119602635482
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10043965582 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x263cafd0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10043965582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 38.pattgen_inactive_level.82456704506526145670160788462353503446847282851823656690922905897642496764419
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10045493610 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x89ececd0, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
  UVM_INFO @ 10045493610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 40.pattgen_inactive_level.20083451196421734037625211826987470231559406955934131520082360882792035394709
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013335276 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x11474c50, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10013335276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```