PATTGEN Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	335.196us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	35.528us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	16.532us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	231.727us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	19.012us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	179.649us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	16.532us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.012us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.883m	17.929ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	2.743ms	50	50	100.00
V2	error	pattgen_error	8.000s	57.975us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.517m	5.325ms	50	50	100.00
V2	alert_test	pattgen_alert_test	4.000s	10.901us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	33.453us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	187.016us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	187.016us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	35.528us	5	5	100.00
		pattgen_csr_rw	3.000s	16.532us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.012us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	50.830us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	35.528us	5	5	100.00
		pattgen_csr_rw	3.000s	16.532us	20	20	100.00
		pattgen_csr_aliasing	3.000s	19.012us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	50.830us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	319.165us	20	20	100.00
		pattgen_sec_cm	2.000s	188.178us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	319.165us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.950m	118.542ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	4.883m	10.006ms	46	50	92.00
		TOTAL			530	570	92.98

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

Test pattgen_stress_all_with_rand_reset has 27 failures.

0.pattgen_stress_all_with_rand_reset.103853515262312419971735695385810379745280150095774240289603619102495690081275
Line 459, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38959729549 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 38959765135 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 38959765135 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 38960125135 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.6379485202441287341840793131215578214174672748507595458834781463444620472423
Line 834, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 156924883955 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 156924936210 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 156924936210 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 156925112682 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 25 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 9 failures:
- Test pattgen_stress_all_with_rand_reset has 9 failures.
  - 4.pattgen_stress_all_with_rand_reset.96710865017165223829087102715774359617470153792986131118801122393892395234561
    Line 577, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32261913423 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 9.pattgen_stress_all_with_rand_reset.665831952435308496346511824367741009897674691035301566655308724194901672069
    Line 465, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49900454095 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 7 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 13.pattgen_inactive_level.29237847150688836104579090872350114498408791770383948294845896640321370313642
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10006416525 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8f2de010, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10006416525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 37.pattgen_inactive_level.26870077827094871784844175096415916332741739868363970640473058214528521737904
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008168703 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf07c7b10, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10008168703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 43.pattgen_inactive_level.99621078515845807716293322183577423351291631340928557649199327004257203198994
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10085682538 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcf9e5e10, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10085682538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 49.pattgen_inactive_level.66621359954049200369306732907407388952499800540389960997552312864900533489176
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10005039591 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xae1fd350, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10005039591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```