PATTGEN Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	168.771us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	116.097us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	14.515us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	1.390ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	78.719us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	17.565us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	14.515us	20	20	100.00
		pattgen_csr_aliasing	2.000s	78.719us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.967m	15.777ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.817m	10.964ms	50	50	100.00
V2	error	pattgen_error	9.000s	20.137us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.833m	27.726ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	12.853us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	19.013us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	184.047us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	184.047us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	116.097us	5	5	100.00
		pattgen_csr_rw	3.000s	14.515us	20	20	100.00
		pattgen_csr_aliasing	2.000s	78.719us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	16.918us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	116.097us	5	5	100.00
		pattgen_csr_rw	3.000s	14.515us	20	20	100.00
		pattgen_csr_aliasing	2.000s	78.719us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	16.918us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	271.331us	20	20	100.00
		pattgen_sec_cm	2.000s	72.843us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	271.331us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.417m	232.223ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	2.883m	10.346ms	47	50	94.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.3651361900826496818547561419497694610452114457640342126787530237754740979248
Line 296, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4125594061 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4125616403 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4125616403 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 4125699737 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.103873916615994843212625910963784060021950806032569947848030973018857986177320
Line 801, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 44848907541 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 44848924204 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 44848924204 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 44848992000 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 20.pattgen_stress_all_with_rand_reset.86260503935147625814995548887145675739157386657315022063296104011262244331981
    Line 424, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25540464376 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 27.pattgen_stress_all_with_rand_reset.96197536615895496756652548298535374365381726881426938068853149278952402526898
    Line 818, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44567741344 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 8.pattgen_inactive_level.25808803626745516185652856195615376038423011027754646244340226469587850769154
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10036417292 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4c088690, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10036417292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 10.pattgen_inactive_level.47799444089082623148486652773968043638789682412170552246246401505373412358039
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10151057056 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x92e987d0, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
  UVM_INFO @ 10151057056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 41.pattgen_inactive_level.22526341832020273941740527544562032781896551898413875534511609031935854952606
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10345853639 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2ce6fb90, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
  UVM_INFO @ 10345853639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```