PATTGEN Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	673.246us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	14.704us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	6.000s	30.396us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	515.333us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	31.570us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	114.740us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	6.000s	30.396us	20	20	100.00
		pattgen_csr_aliasing	4.000s	31.570us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.900m	5.380ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	2.688ms	50	50	100.00
V2	error	pattgen_error	8.000s	36.539us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.917m	2.676ms	50	50	100.00
V2	alert_test	pattgen_alert_test	6.000s	22.682us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	60.553us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	654.161us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	654.161us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	14.704us	5	5	100.00
		pattgen_csr_rw	6.000s	30.396us	20	20	100.00
		pattgen_csr_aliasing	4.000s	31.570us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	41.359us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	14.704us	5	5	100.00
		pattgen_csr_rw	6.000s	30.396us	20	20	100.00
		pattgen_csr_aliasing	4.000s	31.570us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	41.359us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	131.509us	20	20	100.00
		pattgen_sec_cm	4.000s	242.282us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	131.509us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	41.150m	390.710ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	2.517m	10.091ms	48	50	96.00
		TOTAL			533	570	93.51

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.39465675870047818373853597616551386279412606365234860580454210392249334933492
Line 963, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38531979622 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 38531988610 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 38531988610 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 9/10
  UVM_INFO @ 38532091700 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.100166464335080191320363626542225886906095162381213137886749360609809732449246
Line 720, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36341725142 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 36341734333 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 36341734333 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 36341938413 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 16.pattgen_stress_all_with_rand_reset.91573158273613744072032132362861562329941608562662454840005128502291888975574
    Line 1226, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74414231894 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 20.pattgen_stress_all_with_rand_reset.23386632047644516443236265892902921249323445751536167786908014153402605043577
    Line 1029, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48927639591 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 47.pattgen_inactive_level.19302038928179516189035361861804006763769779344691852815357643482914199498169
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10049038323 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3e6dce50, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10049038323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 49.pattgen_inactive_level.53307915929076377982105550330132864500699176857590505424003747856591920506298
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10091481086 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdc4cd310, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10091481086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```