PATTGEN Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	59.181us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	6.000s	18.119us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	14.082us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	127.399us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	7.000s	26.487us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	39.177us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	14.082us	20	20	100.00
		pattgen_csr_aliasing	7.000s	26.487us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.867m	3.950ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	10.045ms	50	50	100.00
V2	error	pattgen_error	3.000s	176.391us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.600m	5.323ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	41.936us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	11.946us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	14.000s	171.083us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	14.000s	171.083us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	6.000s	18.119us	5	5	100.00
		pattgen_csr_rw	7.000s	14.082us	20	20	100.00
		pattgen_csr_aliasing	7.000s	26.487us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	22.661us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	6.000s	18.119us	5	5	100.00
		pattgen_csr_rw	7.000s	14.082us	20	20	100.00
		pattgen_csr_aliasing	7.000s	26.487us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	22.661us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	9.000s	174.440us	20	20	100.00
		pattgen_sec_cm	3.000s	124.807us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	9.000s	174.440us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	36.667m	78.399ms	19	50	38.00
V3		TOTAL			19	50	38.00
	Unmapped tests	pattgen_inactive_level	31.000s	10.204ms	46	50	92.00
		TOTAL			535	570	93.86

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

Test pattgen_stress_all_with_rand_reset has 28 failures.

0.pattgen_stress_all_with_rand_reset.13659777704832809327166981897422317285596538165497402561813752658198141321201
Line 454, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5224858652 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5224868702 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5224868702 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 5224941621 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.115303568515934521945615646038907926862469377989028999011953847337309344340393
Line 297, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 985865324 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 985871487 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 985871487 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 985891895 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 26 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 4.pattgen_stress_all_with_rand_reset.72772340000983318677043880649871875723646428530272531992567435498531322519535
    Line 589, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79343936748 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 16.pattgen_stress_all_with_rand_reset.16700350533678294685315471652982709028513283443550493989189217819909953424351
    Line 323, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6532952175 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 21.pattgen_inactive_level.78932524282522558038639548438177165767659365534021498333617259343215350749817
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10203842989 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfbe96890, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
  UVM_INFO @ 10203842989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 30.pattgen_inactive_level.22900257957381079540203582911007320530280293446863466125479530065233658124970
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 11304632785 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x15cc7e90, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 11304632785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 34.pattgen_inactive_level.62369121016455677528645869005380843660366789779521921451903748787939315408034
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10085675797 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x68d87010, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10085675797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 46.pattgen_inactive_level.30622172005001754100721403247211120785189285305770354472206416288506657414594
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015504149 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x478115d0, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
  UVM_INFO @ 10015504149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```