PATTGEN Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	143.542us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	18.269us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	15.321us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	14.000s	825.781us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	8.000s	155.788us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	22.211us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	15.321us	20	20	100.00
		pattgen_csr_aliasing	8.000s	155.788us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.967m	8.292ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.000m	17.533ms	50	50	100.00
V2	error	pattgen_error	13.000s	129.287us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.933m	4.290ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	47.063us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	42.665us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	14.000s	35.978us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	14.000s	35.978us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	18.269us	5	5	100.00
		pattgen_csr_rw	12.000s	15.321us	20	20	100.00
		pattgen_csr_aliasing	8.000s	155.788us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	46.360us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	18.269us	5	5	100.00
		pattgen_csr_rw	12.000s	15.321us	20	20	100.00
		pattgen_csr_aliasing	8.000s	155.788us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	46.360us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	18.000s	53.628us	20	20	100.00
		pattgen_sec_cm	8.000s	35.802us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	18.000s	53.628us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.900m	2.675s	6	50	12.00
V3		TOTAL			6	50	12.00
	Unmapped tests	pattgen_inactive_level	2.750m	10.022ms	47	50	94.00
		TOTAL			523	570	91.75

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:

Test pattgen_stress_all_with_rand_reset has 41 failures.

0.pattgen_stress_all_with_rand_reset.69941435269842284458197908180193232940280802090494961579364864966735498566877
Line 487, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9014507748 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9014512610 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9014512610 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 9014582610 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.99127422284479141935490618539702839511148925001139445209835147549272792989726
Line 377, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5798980409 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5798999211 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5798999211 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 5799060435 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 39 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 10.pattgen_stress_all_with_rand_reset.86824389613492803550572428959957340553761617526018950980477166001449405281933
    Line 443, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41326822221 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 16.pattgen_stress_all_with_rand_reset.51378632174430929310072261511549263402655145951574599519402332792082982671601
    Line 362, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12585757334 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 0.pattgen_inactive_level.781091442583097851622393964786394922393390755537014420163199110233712761529
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10030225537 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x88dae690, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10030225537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.pattgen_inactive_level.21004548902349185069235806477103782006444353217050107222127501324160371249274
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10002729073 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9bb519d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10002729073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 9.pattgen_inactive_level.108384759006938716269593567090172139694128333828358414589528364006004695865239
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10021974775 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc48e3050, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10021974775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```