PATTGEN Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	17.000s	94.088us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	18.378us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	37.853us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.254ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	18.500us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	74.891us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	37.853us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.500us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	2.749ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	2.634ms	50	50	100.00
V2	error	pattgen_error	9.000s	218.417us	50	50	100.00
V2	stress_all	pattgen_stress_all	6.367m	9.778ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	13.683us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	88.381us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	33.248us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	33.248us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	18.378us	5	5	100.00
		pattgen_csr_rw	3.000s	37.853us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.500us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	46.014us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	18.378us	5	5	100.00
		pattgen_csr_rw	3.000s	37.853us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.500us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	46.014us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	145.174us	20	20	100.00
		pattgen_sec_cm	7.000s	80.391us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	145.174us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	39.283m	472.494ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	12.000s	308.621us	49	50	98.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

0.pattgen_stress_all_with_rand_reset.113600769199532568759506972192648278155774865831462761997534682293930215460397
Line 689, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 101141592032 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 101141608368 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 101141608368 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 101141858370 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.105092090695315915875370916032288282248620903721949404845988758062179706680739
Line 910, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 128999379207 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 128999417703 ps: (cip_base_vseq.sv:759) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 128999417703 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 128999737703 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 8.pattgen_stress_all_with_rand_reset.103632941402340378708356415727274467560275923601344755093414367086065402981519
    Line 1238, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 74799058460 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 40.pattgen_stress_all_with_rand_reset.46352863791654779424489361364528684625858106323330033167492742042012527937482
    Line 446, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33368821920 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 27.pattgen_inactive_level.107911755921907741107601373956458305737265077006407185206749020994819158979053
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10102862326 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8586ed10, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10102862326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```