PATTGEN Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 9.000s 187.671us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 3.000s 49.091us 5 5 100.00
V1 csr_rw pattgen_csr_rw 2.000s 55.485us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 4.000s 595.488us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 2.000s 23.544us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 3.000s 27.968us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 2.000s 55.485us 20 20 100.00
pattgen_csr_aliasing 2.000s 23.544us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.800m 8.581ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.933m 10.524ms 50 50 100.00
V2 error pattgen_error 8.000s 25.792us 50 50 100.00
V2 stress_all pattgen_stress_all 3.633m 10.834ms 50 50 100.00
V2 alert_test pattgen_alert_test 7.000s 10.629us 50 50 100.00
V2 intr_test pattgen_intr_test 3.000s 37.654us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 262.700us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 262.700us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 3.000s 49.091us 5 5 100.00
pattgen_csr_rw 2.000s 55.485us 20 20 100.00
pattgen_csr_aliasing 2.000s 23.544us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 50.100us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 3.000s 49.091us 5 5 100.00
pattgen_csr_rw 2.000s 55.485us 20 20 100.00
pattgen_csr_aliasing 2.000s 23.544us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 50.100us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 3.000s 181.149us 20 20 100.00
pattgen_sec_cm 3.000s 118.385us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 3.000s 181.149us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 30.717m 76.128ms 14 50 28.00
V3 TOTAL 14 50 28.00
Unmapped tests pattgen_inactive_level 5.517m 10.004ms 47 50 94.00
TOTAL 531 570 93.16

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.88 100.00 100.00 100.00 99.16 96.13 -- 100.00 89.95

Failure Buckets

Past Results