PATTGEN Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	187.671us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	49.091us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	55.485us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	595.488us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	23.544us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	27.968us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	55.485us	20	20	100.00
		pattgen_csr_aliasing	2.000s	23.544us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.800m	8.581ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	10.524ms	50	50	100.00
V2	error	pattgen_error	8.000s	25.792us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.633m	10.834ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	10.629us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	37.654us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	262.700us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	262.700us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	49.091us	5	5	100.00
		pattgen_csr_rw	2.000s	55.485us	20	20	100.00
		pattgen_csr_aliasing	2.000s	23.544us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	50.100us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	49.091us	5	5	100.00
		pattgen_csr_rw	2.000s	55.485us	20	20	100.00
		pattgen_csr_aliasing	2.000s	23.544us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	50.100us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	181.149us	20	20	100.00
		pattgen_sec_cm	3.000s	118.385us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	181.149us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.717m	76.128ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	5.517m	10.004ms	47	50	94.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.37368919648368548119768660843516211993980124939250322210440531765846820457745
Line 500, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 39970668260 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 39970702568 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 39970702568 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 39970785902 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.51675042952409770217799012628649603002729345981808871117955906255427467460496
Line 437, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5312542089 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5312543847 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5312543847 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 5312633847 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 39.pattgen_stress_all_with_rand_reset.26613042949836557668382207429446456936432489510940483997542971383334397953915
    Line 616, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79312286453 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 40.pattgen_stress_all_with_rand_reset.41450937180521110282415350766675922642053953862623653909025946403297473173176
    Line 496, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65756826484 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 5.pattgen_inactive_level.92210461364182118687723418934816258883713516998303722521846596684167526487545
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10019589138 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4323cd90, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10019589138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 11.pattgen_inactive_level.75770607622910070897159257218014946047799480264729526312556602292666546203197
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10354936177 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3093c390, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
  UVM_INFO @ 10354936177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 30.pattgen_inactive_level.63578593106559343804218374728650711768619306253230116276902474165580742235188
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003914863 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x12f62f90, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10003914863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```